Motorola DSP56367 User Manual page 76

Specifications
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
No.
21 Delay from WR assertion to interrupt request deassertion for
level sensitive fast interrupts
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
SRAM WS ≥ 4
•
24 Duration for IRQA assertion to recover from Stop state
25 Delay from IRQA assertion to fetch of first instruction
2, 3
(when exiting Stop)
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
enabled
(OMR Bit 6 = 0)
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
not enabled (OMR Bit 6 = 1)
• PLL is active during Stop (PCTL
Bit 17 = 1) (Implies No Stop Delay)
26 Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
enabled
(OMR Bit 6 = 0)
• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
not enabled
(OMR Bit 6 = 1)
• PLL is active during Stop (PCTL
Bit 17 = 1) (implies no Stop delay)
3-10
Characteristics
1
2, 3
DSP56367
Expression
(WS + 3.5) × T
– 10.94
C
(WS + 3.5) × T
– 10.94
C
(WS + 3) × T
– 10.94
C
(WS + 2.5) × T
– 10.94
C
PLC × ET × PDF + (128 K −
C
PLC/2) × T
C
PLC × ET × PDF + (23.75 ± 0.5)
C
× T
C
(8.25 ± 0.5) × T
C
PLC × ET × PDF + (128K −
C
PLC/2) × T
C
PLC × ET × PDF + (20.5 ± 0.5)
C
× T
C
5.5 × T
C
Min Max Unit
ns
— Note 7
— Note 7
— Note 7
— Note 7
4.9 —
— — ms
— — ms
64.6 72.9 ns
— — ms
— — ms
45.8 — ns
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