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The SHI interrupt vector table is shown in Table 9-1 and the exception priorities generated by
the SHI are shown in Table 9-2.
Program Address
VBA:$0040
VBA:$0042
VBA:$0044
VBA:$0048
VBA:$004A
VBA:$004C
Priority
Highest
Lowest
9.5.1
SHI INPUT/OUTPUT SHIFT REGISTER (IOSR)—HOST SIDE
The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel
and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both
directions (read and write). In compliance with the I
in and out MSB first. In 8-bit data transfer modes, the most significant byte of the IOSR is
used as the shift register. In 16-bit data transfer modes, the two most significant bytes become
the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the IOSR
(see Figure 9-5).
MOTOROLA
Table 9-1 SHI Interrupt Vectors
SHI Transmit Data
SHI Transmit Underrun Error
SHI Receive FIFO Not Empty
SHI Receive FIFO Full
SHI Receive Overrun Error
SHI Bus Error
Table 9-2 SHI Internal Interrupt Priorities
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
SHI Receive FIFO Full
SHI Transmit Data
SHI Receive FIFO Not Empty
DSP56367
Serial Host Interface Programming Model
Interrupt Source
Interrupt
2
C and SPI bus protocols, data is shifted
Serial Host Interface
9-7
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