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Channel B
Channel A
Non-Audio Data
Channel B
Channel A
Non-Audio Data
Channel B
Channel A
Non-Audio Data
Channel B
Channel A
Non-Audio Data
Non-audio data bits change
from frame to frame
Figure 12-6 Examples of data organization in memory
12.6.5
DAX OPERATION DURING STOP
The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are
active. While the DSP is in the stop state, the DAX will remain in the individual reset state
and the status flags are initialized as described for resets. No DAX control bits are affected.
The DAX should be disabled before the DSP enters the stop state.
12.7
GPIO (PORT D) - PINS AND REGISTERS
The Port D GPIO functionality of the DAX is controlled by three registers: Port D Control
Register (PCRD), Port D Direction Register (PRRD) and Port D Data Register (PDRD).
MOTOROLA
$00000B
$00000A
$000009
$000008
$000007
$000006
$000005
$000004
$000003
$000002
$000001
$000000
DSP56367
Digital Audio Transmitter
GPIO (PORT D) - Pins and Registers
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Non-audio data bits do not
change from frame to frame
$00000B
$00000A
$000009
$000008
$000007
$000006
$000005
$000004
$000003
$000002
$000001
$000000
12-15
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