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Serial Host Interface
Serial Host Interface Internal Architecture
•
Generate ACK signal following a byte receive
•
Inspect ACK signal following a byte transmit
•
Directly operate with 8-, 16- and 24-bit words
•
Generate vectored interrupts separately for receive and transmit events and update
status bits
•
Generate a separate vectored interrupt for a receive exception
•
Generate a separate vectored interrupt for a bus error exception
•
Generate the clock signal (in master mode)
•
Trigger DMA interrupts to service the transmit and receive events
9.2
SERIAL HOST INTERFACE INTERNAL ARCHITECTURE
The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The
DSP uses the SHI as a normal memory-mapped peripheral using standard polling or interrupt
programming techniques and DMA transfers. Memory mapping allows DSP communication
with the SHI registers to be accomplished using standard instructions and addressing modes.
In addition, the MOVEP instruction allows interface-to-memory and memory-to-interface
data transfers without going through an intermediate register. The DMA controller may be
used to service the receive or transmit data path. The single master configuration allows the
DSP to directly connect to dumb peripheral devices. For that purpose, a programmable
baud-rate generator is included to generate the clock signal for serial transfers. The host side
invokes the SHI for communication and data transfer with the DSP through a shift register
that may be accessed serially using either the I
the SHI block diagram.
9-2
2
C or the SPI bus protocols. Figure 9-1 shows
DSP56367
MOTOROLA
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