Motorola DSP56367 User Manual page 9

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10.3.1 ESAI Transmitter Clock Control Register (TCCR) . . . . . . . . . . . . . . . . . . 10-9
10.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7-TPM0) - Bits 0-7 10-10
10.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8 . . . . . . . . . . . . . . . . 10-12
10.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4-TDC0) - Bits 9-13 . 10-12
10.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14-17 10-13
10.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 . . . . . . . . . . . . . . . . 10-14
10.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 . . . . . . . . . . . . 10-14
10.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 . 10-14
10.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 . . . . . . . . 10-14
10.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22. . . . . 10-15
10.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 10-15
10.3.2 ESAI Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0. . . . . . . . . . . . . . . . . . . . 10-15
10.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1. . . . . . . . . . . . . . . . . . . . 10-16
10.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2. . . . . . . . . . . . . . . . . . . . 10-16
10.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3. . . . . . . . . . . . . . . . . . . . 10-17
10.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4. . . . . . . . . . . . . . . . . . . . 10-17
10.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5. . . . . . . . . . . . . . . . . . . . 10-18
10.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6 . . . . . . . . . . . . . . . . . 10-18
10.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7 . . . . . . . . . . 10-18
10.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-910-19
10.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-1410-21
10.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15. . . . . . . . . . . . . . 10-22
10.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 . . . . . . 10-24
10.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17 . . . . . . . . . . . 10-24
10.3.2.14 TCR Reserved Bit - Bits 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19 . . . . . . . . . . . . 10-24
10.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 . . . . . . . . 10-25
10.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21. . . 10-25
10.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22 . . . . . . . . . . . . . . . . . . 10-25
10.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 . . . . . . . . . 10-25
10.3.3 ESAI Receive Clock Control Register (RCCR) . . . . . . . . . . . . . . . . . . . . 10-26
10.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7-RPM0) - Bits 7-0 10-26
10.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8 . . . . . . . . . . . . . . . . 10-26
10.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4-RDC0) - Bits 9-13 . 10-26
10.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-1710-27
10.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18 . . . . . . . . . . . . . . . . 10-27
10.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19. . . . . . . . . . . . 10-27
10.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 . 10-28
10.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 . . . . . . . . 10-28
10.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 . . . . 10-28
10.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 2310-29
10.3.4 ESAI Receive Control Register (RCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
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