Esai Programming Model - Motorola DSP56367 User Manual

or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as
the serial flag 2 pin. For further information on pin mode and definition, see Table 10-9 and
on receiver clock signals see Table 10-1.
When this pin is configured as serial flag pin, its direction is determined by the RHCKD bit in
the RCCR register. When configured as the output flag OF2, this pin reflects the value of the
OF2 bit in the SAICR register, and the data in the OF2 bit shows up at the pin synchronized to
the frame sync being used by the transmitter and receiver sections. When configured as the
input flag IF2, the data value at the pin is stored in the IF2 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
HCKR may be programmed as a general-purpose I/O pin (PC2) when the ESAI HCKR
function is not being used.
10.3

ESAI PROGRAMMING MODEL

The ESAI can be viewed as five control registers, one status register, six transmit data
registers, four receive data registers, two transmit slot mask registers, two receive slot mask
registers and a special-purpose time slot register. The following paragraphs give detailed
descriptions and operations of each bit in the ESAI registers.
The ESAI pins can also function as GPIO pins (Port C), described in Section 10.5, "GPIO -
Pins and Registers".
10.3.1 ESAI TRANSMITTER CLOCK CONTROL REGISTER
(TCCR)
The read/write Transmitter Clock Control Register (TCCR) controls the ESAI transmitter
clock generator bit and frame sync rates, the bit clock and high frequency clock sources and
the directions of the HCKT, FST and SCKT signals. (See Figure 10-2). In the synchronous
MOTOROLA
Enhanced Serial Audio Interface (ESAI)
DSP56367
ESAI Programming Model
10-9