Esai Receive Shift Registers - Motorola DSP56367 User Manual

Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
10.3.7

ESAI RECEIVE SHIFT REGISTERS

The receive shift registers (see Figure 10-13 and Figure 10-14) receive the incoming data
from the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock
when the associated frame sync I/O is asserted. Data is assumed to be received MSB first if
RSHFD=0 and LSB first if RSHFD=1. Data is transferred to the ESAI receive data registers
after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the slot length
control bits in the RCR register.
10.3.8 ESAI RECEIVE DATA REGISTERS (RX3, RX2, RX1, RX0)
RX3, RX2, RX1 and RX0 are 24-bit read-only registers that accept data from the receive shift
registers when they become full (see Figure 10-13 and Figure 10-14). The data occupies the
most significant portion of the receive data registers, according to the ALC control bit setting.
The unused bits (least significant portion, and 8 most significant bits when ALC=1) read as
zeros. The DSP is interrupted whenever RXx becomes full if the associated interrupt is
enabled.
10.3.9 ESAI TRANSMIT SHIFT REGISTERS
The transmit shift registers contain the data being transmitted (see Figure 10-13 and Figure
10-14). Data is shifted out to the serial transmit data pins by the selected (internal/external) bit
clock when the associated frame sync I/O is asserted. The number of bits shifted out before
the shift registers are considered empty and may be written to again can be 8, 12, 16, 20, 24 or
32 bits (determined by the slot length control bits in the TCR register). Data is shifted out of
these registers MSB first if TSHFD=0 and LSB first if TSHFD=1.
10.3.10 ESAI TRANSMIT DATA REGISTERS (TX5, TX4, TX3,
TX2,TX1,TX0)
TX5, TX4, TX3, TX2, TX1 and TX0 are 24-bit write-only registers. Data to be transmitted is
written into these registers and is automatically transferred to the transmit shift registers (see
Figure 10-13 and Figure 10-14). The data written (8, 12, 16, 20 or 24 bits) should occupy the
most significant portion of the TXx according to the ALC control bit setting. The unused bits
(least significant portion, and the 8 most significant bits when ALC=1) of the TXx are don't
care bits. The DSP is interrupted whenever the TXx becomes empty if the transmit data
register empty interrupt has been enabled.
10-44 DSP56367 MOTOROLA