Motorola DSP56F801 Manuals

Manuals and User Guides for Motorola DSP56F801. We have 2 Motorola DSP56F801 manuals available for free PDF download: User Manual, Hardware User Manual

Motorola DSP56F801 User Manual

Motorola DSP56F801 User Manual (782 pages)

Brand: Motorola | Category: Signal Processors | Size: 9 MB

Table of Contents

Table of Contents
5
DSP56F801/803/805/807 Overview
39
Introduction
41
DSP56800 Family Description
43
Manual Organization
45
Manual Conventions
47
Pin Conventions
48
Architectural Overview
49
DSP56F801 Functional Block Diagram
49
DSP56F803 Functional Block Diagram
50
DSP56F805 Functional Block Diagram
51
DSP56F807 Functional Block Diagram
52
Feature Matrix
53
DSP56800 Core Description
54
DSP56800 Core Differences
54
DSP56800 Core Block Diagram
55
DSP56800 Core Block Diagram
56
DSP56800 Bus Block Diagram
57
Data Arithmetic Logic Unit (Data ALU)
58
Address Generation Unit (AGU)
59
Program Controller and Hardware Looping Unit
59
Bit Manipulation Unit
59
Address and Data Buses
60
On-Chip Emulation (Once) Module
61
On-Chip Clock Synthesis Block
61
DSP56F800 Address and Data Buses
61
Oscillators
62
Pll
62
Resets
63
Core Voltage Regulator
63
Ipbus Bridge
63
Memory Modules
63
Program Flash
65
Program RAM
65
Data Flash
65
Data RAM
65
DSP56F801 Peripheral Blocks
66
DSP56F803 Peripheral Blocks
66
DSP56F805 Peripheral Blocks
67
DSP56F807 Peripheral Blocks
68
Peripheral Descriptions
68
External Memory Interface
68
General Purpose Input/Output Port (GPIO)
69
Serial Peripheral Interface (SPI)
69
Cop/Watchdog Timer & Modes of Operation Module
70
Jtag/Once Port
70
Quadrature Decoder
70
Quad Timer Module
71
Pulse Width Modulator (PWM) Module
72
Analog-To-Digital Conversion (ADC)
72
ADC & PWM Synchronization Feature
73
Serial Communications Interface (SCI)
73
Motorola Scannable Controller Area Network (MSCAN) Module
74
Peripheral Interrupts
74
DSP56800 Programming Model
74
Register Programming Model for the DSP56800
75
Pin Descriptions
77
Introduction
79
Functional Group Pin Allocations
79
Interrupt and Program Control Signals
79
DSP56F801 Signals Identified by Functional Group
80
DSP56F803 Signals Identified by Functional Group
81
DSP56F805 Signals Identified by Functional Group
82
DSP56F807 Signals Identified by Functional Group
83
Power and Ground Signals
84
Power Inputs
84
Supply Capacitors and VPP
84
DSP56F801 Power and Ground Pins
85
DSP56F803 Power and Ground Pins
85
DSP56F805 Power and Ground Pins
86
DSP56F807 Power and Ground Pins
86
Clock and Phase Lock Loop Signals
87
Address, Data, and Bus Control Signals
88
Address Bus Signals
88
Data Bus Signals
89
Bus Control Signals
89
Interrupt and Program Control Signals
90
GPIO Signals
91
Dedicated General Purpose Input/Output (GPIO) Signals
91
Pulse Width Modulator (PWM) Signals
92
Pulse Width Modulator (PWMA and PWMB) Signals
92
Serial Peripheral Interface (SPI) Signals
93
Quadrature Decoder Signals
94
Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
94
Serial Communications Interface (SCI) Signals
95
CAN Signals
95
Serial Communications Interface (SCI0 and SCI1) Signals
95
CAN Module Signals
95
Analog to Digital Converter (ADC) Signals
96
Quad Timer Module Signals
96
Analog to Digital Converter (ADCA and ADCB) Signals
96
Jtag/Once
97
Jtag/On-Chip Emulation (Once) Signals
97
Memory and Operating Modes
99
Memory Map
101
DSP56F801/803/805/807 Memory Map Description
101
Chip Memory Configurations
101
Program Memory Map for DSP56F801/803/805/807
102
Data Memory
103
Data Memory Map for DSP56F801/803/805/807
103
Bus Control Register (BCR)
105
Reserved Bits-Bits 15-10 and 8
105
Drive Bit (DRV)-Bit 9
105
Wait State Data Memory (WSX[3:0])-Bits 7-4
106
Wait State P Memory (WSP[3:0])-Bits 3-0
106
Operating Mode Register (OMR)
106
Programming WSX[3:0] Bits for Wait States
106
Programming WSP[3:0] Bits for Wait States
106
Looping Status
107
Saturation (SA)-Bit 4
108
MAC Unit Outputs with Saturation Mode Enabled (SA = 1)
108
External X Memory (EX)-Bit 3
109
Operating Mode B (MB)-Bit 1
109
Operating Mode a (MA)-Bit 0
109
Core Configuration Memory Map
109
On-Chip Peripheral Memory Map
110
DSP56800 On-Chip Core Configuration Register Memory Map
110
Data Memory Peripheral Address Map
112
System Control Registers Address Map
113
Program Flash Interface Unit #2 Registers Address Map
113
Quad Timer a Registers Address Map
114
Quad Timer B Registers Address Map
115
Quad Timer C Registers Address Map
116
Quad Timer D Registers Address Map
117
CAN Registers Address Map
118
PWMA Registers Address Map
119
PWMB Registers Address Map
119
Quadrature Decoder #0 Registers Address Map
120
Quadrature Decoder #1 Registers Address Map
120
Interrupt Controller Registers Address Map
121
ADCA Registers Address Map
121
ADCB Registers Address Map
122
SCI0 Registers Address Map
122
SCI1 Registers Address Map
122
SPI Registers Address Map
123
COP Registers Address Map
123
Program Flash Interface Unit Registers Address Map
123
Data Flash Interface Unit Registers Address Map
124
Boot Flash Interface Unit Registers Address Map
124
Clock Generation Registers Address Map
125
GPIO Port a Registers Address Map
125
GPIO Port B Registers Address Map
125
Program Memory
126
GPIO Port D Registers Address Map
126
GPIO Port E Registers Address Map
126
DSP56800 Operating Modes
127
Mode 0-Single Chip Mode: Start-Up
127
DSP56F801/803/805/807 Program Memory Chip Operating Modes
127
Modes 1 and 2
128
Mode 3-External
128
Boot Flash Operation
128
Example Contents of Data Stream to be Loaded from Serial EEPROM
129
Executing Programs from XRAM
130
DSP56800 Reset and Interrupt Vectors
130
Reset and Interrupt Priority Structure
130
Reset and Interrupt Vector Map
131
Memory Architecture
133
DSP803/805/807 On-Board Address and Data Buses
133
Interrupt Controller (ITCN)
135
Introduction
137
DSP56F801/803/805/807 Interrupt Priority Register
138
ITCN Register Summary
139
Interrupt Programming
139
Priority Level and Vector Assignments
140
Interrupt Vectors and Addresses
140
Register Definitions
143
Group Priority Register 13 (GPR13)
145
Group Priority Register 14 (GPR14)
145
Group Priority Register 15 (GPR15)
145
Test Interrupt Request Registers 0-3 (TIRQO-TIQ3)
146
Test Interrupt Request Register 0 (TIRQ0)
146
Test Interrupt Request Register 1 (TIRQ1)
146
Test Interrupt Request Register 2 (TIRQ2)
146
Test Interrupt Request Register 3 (TIRQ3)
146
Test Control and Status Register (TCSR)
147
Test Interrupt Source Register 0 (TISR0)
147
Test Interrupt Source Register 1 (TISR1)
147
Test Interrupt Source Register 2 (TISR2)
147
Test Interrupt Source Register 3 (TISR3)
147
Any IRQ Flag Bit (IRQ0)-Bit 15
148
Current Vector Output (Vector[5:0])-Bits 13-8
148
Test Mode (TMODE)-Bit 7
148
Peripheral Test Mode (PTM)-Bit 6
148
Field Specifying the Interrupt Acknowledge Level During PTM
148
Flash Memory Interface
149
Introduction
151
Features
151
Register Summary
152
General Flash Description
153
Truth Table
154
IFREN Truth Table
154
Internal Flash Timing Variables
154
Flash Timing Relationships
155
Flash Program Cycle
155
Flash Erase Cycle
155
Program Flash (PFLASH)
156
Flash Mass Erase Cycle
156
Program Flash Block Diagram
157
Data Flash (DFLASH)
157
Program Flash Block Integration
157
Data Flash Block Diagram
158
Boot Flash (BFLASH)
158
Data Flash Block Integration
158
Boot Flash Main Block Organization
158
Boot Flash Block Diagram
159
Program/Data/Boot Flash Interface Unit Features
159
Program/Data/Boot Flash Modes
159
Boot Flash Block Integration
159
Functional Description of the PFIU, DFIU and BFIU
160
Flash Programming and Erase Models
161
Intelligent Word Programming
161
Dumb Word Programming
162
Intelligent Erase Operation
163
Memory Map & Register Definitions
163
Flash Program Enable Register (FIU_PE)
166
Flash Erase Enable Register (FIU_EE)
167
Flash Address Register (FIU_ADDR)
168
Flash Data Register (FIU_DATA)
168
Flash Interrupt Enable Register (FIU_IE)
169
Flash Interrupt Source Register (FIU_IS)
169
Flash Interrupt Pending Register (FIU_IP)
171
Flash Interface Unit Timeout Registers
176
External Memory Interface
179
Introduction
181
External Memory Port Architecture
181
Pin Descriptions
181
Register Summary
182
Port a Description
182
Reserved Bits-Bits 15-10 and 8
182
Drive (DRV)-Bit 9
182
DSP56F801/803/805/807 User's Manual
182
Wait State X Data Memory (WSX[3:0])-Bits 7-4
183
Wait State P Memory (WSP[3:0])-Bits 3-0
183
Programming WSP[3:0] and WSX[3:0] Bits for Wait States
183
Bus Operation (Read/Write-Zero Wait States)
184
Bus Operation (Read/Write-Four Wait States)
184
Pins in Different Processing States
185
General Purpose Input/Output (GPIO)
187
Introduction
189
Block Diagram Showing DSP56F801 GPIO Connections
190
Block Diagram Showing DSP56F803/805/807 GPIO Connections
191
Bit-Slice View of the GPIO Logic
192
GPIO Interrupts
193
Edge Detector Circuit
193
GPIO Register Summary
194
GPIO Interrupt Assert Functionality
194
GPIO Registers with Their Reset Values
194
GPIO Pull-Up Enable Functionality
195
Chip Specific Configurations
196
Programming Model
196
GPIO Data Transfers between GPIO Pin and Ipbus
196
GPIO Assignments
196
Pull-Up Enable Register (PUR)
197
Data Register (DR)
197
Data Direction Register (DDR)
197
Peripheral Enable Register (PER)
198
Interrupt Assert Register (IAR)
198
Interrupt Enable Register (IENR)
199
Interrupt Polarity Register (IPOLR)
199
Interrupt Edge Sensitive Register (IESR)
200
GPIO Programming Algorithms
200
Motorola Scalable Controller Area Network (MSCAN)
203
Introduction
205
Features
205
Pin Definitions
206
CAN System
207
Block Diagram
208
Register Summary
208
Register Map
209
MSCAN Register Organization
210
Functional Description
212
Message Storage
212
User Model for Message Buffer Organization
213
Message Transmit Background
214
Transmit Structures
214
Receive Structures
215
Identifier Acceptance Filter
216
Protocol Violation Protection
221
Clock System
221
MSCAN Clocking Scheme
222
Segments Within the Bit Time
223
Time Segment Syntax
223
Register Descriptions
224
MSCAN Time Segment Settings When CLKSRC = 1 (Ipbus Clock)
224
MSCAN Control Register 0 (CANCTL0)
225
Reserved Bits-Bits 15-8
227
MSCAN Control Register 1 (CANCTL1)
227
CAN Enable (CANE)-Bit 7
227
Loop Back Self Test Mode (LOOPB)-Bit 2
228
MSCAN Clock Source (CLKSRC)-Bit 0
228
MSCAN Bus Timing Register 0 (CANBTR0)
228
Reserved Bits-Bits 15-8
229
Synchronization Jump Width (SJW[1:0])-Bits 7-6
229
Baud Rate Prescaler (BRP[5:0])-Bits 5-0
229
Synchronization Jump Width
229
Examples of Baud Rate Prescaler
229
MSCAN Bus Timing Register 1 (CANBTR1)
230
Time Segment 2 (TSEG22-TSEG20)-Bits 6-4
231
Time Segment 2 Values
231
Time Segment 1 Values
231
MSCAN Receiver Flag Register (CANRFLG)
232
Reserved Bits-Bits 15-8
232
Wake-Up Interrupt Flag (WUPIF)-Bit 7
233
Receiver Warning Interrupt Flag (RWRNIF)-Bit 6
233
Transmitter Warning Interrupt Flag (TWRNIF)-Bit 5
233
Receiver Error Passive Interrupt Flag (RERRIF)-Bit 4
233
Transmitter Error Passive Interrupt Flag (TERRIF)-Bit 3
234
Bus-Off Interrupt Flag (BOFFIF)-Bit 2
234
Overrun Interrupt Flag (OVRIF)-Bit 1
234
MSCAN Receiver Interrupt Enable Register (CANRIER)
235
Reserved Bits-Bits 15-8
235
Wake-Up Interrupt Enable (WUPIE)-Bit 7
235
Receiver Warning Interrupt Enable (RWRNIE)-Bit 6
235
Transmitter Warning Interrupt Enable (TWRNIE)-Bit 5
235
Transmitter Error Passive Interrupt Enable (TERRIE)-Bit 3
236
Bus-Off Interrupt Enable (BOFFIE)-Bit 2
236
Overrun Interrupt Enable (OVRIE)-Bit 1
236
Receiver Full Interrupt Enable (RXFIE)-Bit 0
236
MSCAN Transmitter Flag Register (CANTFLG)
236
DSP56F801/803/805/807 User's Manual
236
Reserved Bits-Bits 15-7 and 3
237
Transmitter Buffer Empty (TXE[2:0])-Bits 2-0
237
MSCAN Transmitter Control Register (CANTCR)
237
Abort Request (ABTRQ[2:0])-Bits 6-4
238
Transmitter Empty Interrupt Enable (TXEIE[2:0])-Bits 2-0
238
MSCAN Identifier Acceptance Control Register (CANIDAC)
238
Reserved Bits-Bits 15-6 and 3
238
Identifier Acceptance Mode (IDAM[1:0])-Bits 5-4
238
Identifier Acceptance Mode Settings
239
Identifier Acceptance Hit Indication
239
MSCAN Receive Error Counter Register (CANRXERR)
240
MSCAN Transmit Error Counter Register (CANTXERR)
240
MSCAN Identifier Acceptance Registers (CANIDAR0-7)
240
Acceptance Code Bits (AC[7:0])-Bits 7-0
241
MSCAN Identifier Mask Registers (CANIDMR0-7)
241
Acceptance Mask Bits (AM[7:0])-Bits 7-0
242
Programmer's Model of Message Storage
242
Message Buffer Organization for Peripheral Address Locations
243
Identifier Registers (IDR0-3)
244
Data Segment Registers (DSR0-7)
246
Data Length Register (DLR)
247
Transmit Buffer Priority Register (TBPR)
248
Data Length Codes
248
Modes of Operation
249
Normal Modes
249
Special Modes
249
Emulation Modes
249
Security Modes
249
Low Power Options
249
Run Mode
250
Wait Mode
250
MSCAN Vs. CPU Operating Modes
250
Stop Mode
251
Sleep Mode
251
Sleep Request/Acknowledge Cycle
252
Soft Reset Mode
254
Power down Mode
254
Programmable Wake-Up Function
254
Interrupt Operation
255
Interrupt Acknowledge
256
Interrupt Sources
257
Recovery from Stop or Wait
257
MSCAN Interrupt Sources
257
Analog-To-Digital Converter (ADC)
259
Introduction
261
Features
261
Functional Description
262
ADC Block Diagram
262
Differential Inputs
263
Typical Connections for Differential Measurements
265
Timing
266
ADC Timing
266
Pin Descriptions
267
Analog Input Pins (AN0-AN7)
267
Equivalent Analog Input Circuit
267
Voltage Reference Pin (VREF)
268
Supply Pins
268
Register Summary
268
Register Definitions
269
ADC Control Register 1 (ADCR1)
269
Reserved Bits-Bits 15 and 3
269
Stop (STOP)-Bit 14
269
START Conversion (START)-Bit 13
270
SYNC Select (SYNC)-Bit 12
270
End of Scan Interrupt Enable (EOSIE)-Bit 11
270
Zero Crossing Interrupt Enable (ZCIE)-Bit 10
270
Low Limit Interrupt Enable (LLMTIE)-Bit 9
271
High Limit Interrupt Enable (HLMTIE)-Bit 8
271
Channel Configure (CHNCFG[3:0])-Bits 7-4
271
ADC Control Register 2 (ADCR2)
273
Reserved Bits-Bits 15-4
273
Clock Divisor Select (DIV[3:0])-Bits 3-0
273
ADC Zero Crossing Control Register (ADZCC)
273
ADC Channel List Registers (ADLST1 & ADLST2)
274
ADC Input Conversion for Sample Bits
274
ADC Sample Disable Register (ADSDIS)
275
ADC Core
275
Test (TEST[1:0])-Bits 15-14
276
Reserved Bits-Bits 13-8
276
Disable Sample (DS[7:0])-Bits 7-0
276
ADC Status Register (ADSTAT)
276
Conversion in Progress (CIP)-Bit 15
277
Reserved Bits-Bits 14-12
277
End of Scan Interrupt (EOSI)-Bit 11
277
Zero Crossing Interrupt (ZCI)-Bit 10
277
Low Limit Interrupt (LLMTI)-Bit 9
278
High Limit Interrupt (HLMTI)-Bit 8
278
Ready Channel 7-0 (RDY[7:0])-Bits 7-0
278
ADC Limit Status Register (ADLSTAT)
278
ADC Interrupt
278
ADC Zero Crossing Status Register (ADZCSTAT)
279
ADC Result Registers (ADRSLT0-7)
280
Sign Extend (SEXT)-Bit 15
280
Digital Result of the Conversion (RSLT[11:0])-Bits 14-3
280
Reserved Bits-Bits 2-0
281
Result Register Data Manipulation
281
ADC Low and High Limit Registers (ADLLMT0-7) and (ADHLMT0-7)
282
ADC Offset Registers (ADOFS0-7)
283
Starting a Conversion if Status of ADC Is Unknown
283
Introduction
287
Features
287
Pin Descriptions
287
Phase a Input (PHASEA)
288
Phase B Input (PHASEB)
288
Index Input (INDEX)
288
Home Switch Input (HOME)
288
Register Summary
288
Functional Description
289
Positive Versus Negative Direction
289
Block Diagram
290
Glitch Filter
290
Edge Detect State Machine
290
Position Counter
291
Position Difference Counter
291
Position Difference Counter Hold
291
Revolution Counter
291
Pulse Accumulator Functionality
292
Watchdog Timer
292
Prescaler for Slow or Fast Speed Measurement
292
Modes
293
Holding Registers and Initializing Registers
293
Switch Matrix for Inputs to the Timer
293
Enable HOME to Initialize Position Counters UPOS and LPOS (HIP)-Bit 13
294
Register Definitions
294
Decoder Control Register (DECCR)
294
HOME Signal Transition Interrupt Request (HIRQ)-Bit 15
294
HOME Interrupt Enable (HIE)-Bit 14
294
Software Triggered Initialization of Position Counters UPOS and LPOS
295
Watchdog Enable (WDE)-Bit 2
297
Filter Interval Register (FIR)
297
Filter Delay Register (FIR)
297
Watchdog Time-Out Register (WTR)
298
Position Difference Counter Register (POSD)
298
Position Difference Hold Register (POSDH)
299
Revolution Counter Register (REV)
299
Revolution Hold Register (REVH)
300
Upper Position Counter Register (UPOS)
300
Lower Position Counter Register (LPOS)
300
Upper Position Hold Register (UPOSH)
301
Lower Position Hold Register (LPOSH)
301
Upper Initialization Register (UIR)
301
Lower Initialization Register (LIR)
301
Input Monitor Register (IMR)
302
Reserved Bits-15-8
302
FPHA-Bit 7
302
FPHB-Bit 6
302
PHA-Bit 3
302
PHB-Bit 2
302
INDEX-Bit 1
303
HOME-Bit 0
303
Test Register (TSTREG)
303
Test Mode Enable (TEN)-Bit 15
303
Test Counter Enable (TCE)-Bit 14
303
Count-Bits 7-0
304
Pulse Width Modulator Module (PWM)
305
Introduction
307
Features
307
PWM Block Diagram
308
Pin Descriptions
309
PWM0-PWM5 Pins
309
FAULT0-FAULT3 Pins
309
IS0-IS2 Pins
309
Register Summary
309
Functional Description
310
Block Diagram
310
Prescaler
310
PWM Generator
310
Alignment
311
Period
311
Center-Aligned PWM Output
311
Edge-Aligned PWM Output
311
Duty Cycle
312
Center-Aligned PWM Period
312
Edge-Aligned PWM Period
312
Center-Aligned PWM Pulse Width
313
PWM Value and Underflow Conditions
313
Independent or Complementary Channel Operation
314
Edge-Aligned PWM Pulse Width
314
Complementary Channel Pairs
315
Typical 3 Phase AC Motor Drive
315
Deadtime Generators
316
Deadtime Insertion, Center Alignment
317
Deadtime at Duty Cycle Boundaries
317
Top/Bottom Correction
318
Deadtime and Small Pulse Widths
318
Deadtime Distortion
319
Manual Correction
320
Correction Method Selection
320
Manual Correction
321
Top/Bottom Manual Correction
321
Internal Correction Logic When ISENS[1:0] = 0X
321
Current-Status Sense Scheme for Deadtime Correction
322
Current-Sensing Correction
323
Output Voltage Waveforms
323
Top/Bottom Current-Sense Correction
323
Output Polarity
325
Correction with Positive Current
325
Correction with Negative Current
325
Software Output Control
326
PWM Polarity
326
Setting OUT0 with OUTCTL Set in Complementary Mode
327
Clearing OUT0 with OUTCTL Set in Complementary Mode
328
Setting OUTCTL with OUT0 Set in Complementary Mode
328
PWM Generator Loading
329
Load Enable
329
Load Frequency
329
Full Cycle Reload Frequency Change
329
Reload Flag
330
Half Cycle Reload Frequency Change
330
PWMF Reload Interrupt Request
330
Full-Cycle Center-Aligned PWM Value Loading
330
Full-Cycle Center-Aligned Modulus Loading
331
Half-Cycle Center-Aligned PWM Value Loading
331
Half-Cycle Center-Aligned Modulus Loading
331
Synchronization Output
332
Edge-Aligned PWM Value Loading
332
Edge-Aligned Modulus Loading
332
PWMEN and PWM Pins in Independent Operation (OUTCTL0-5 = 0)
333
PWMEN and PWM Pins in Complementary Operation
333
Fault Protection
334
Fault Mapping
334
Fault Pin Filter
335
Automatic Fault Clearing
335
Manual Fault Clearing
335
Manual Fault Clearing (Example 1)
336
Manual Fault Clearing (Example 2)
336
Interrupts
337
Register Descriptions
337
PWM Control Register (PMCTL)
337
Load Frequency Bits (LDFQ[3:0])-Bits 15-12
337
PWM Prescaler
339
Load Okay Bit (LDOK)-Bit 1
340
PWM Enable Bit (PWMEN)-Bit 0
340
PWM Fault Control Register (PMFCTL)
340
Reserved Bits-Bits 15-8
340
Faultx Pin Interrupt Enable Bit (Fiex)-Bits 7, 5, 3, 1
341
Faultx Pin Clearing Mode Bit (Fmodex)-Bits 6, 4, 2, 0
341
PWM Fault Status & Acknowledge Register (PMFSA)
341
Faultx Pin Bit (Fpinx)-Bits 15, 13, 11, 9
341
Faultx Pin Flag (Fflagx)-Bits 14, 12, 10, 8
342
Reserved Bit-Bit 7
342
Dead Time X (Dtx)-Bits 5-0
342
PWM Output Control Register (PMOUT)
342
Reserved Bits-Bits 14 and 7-6
343
Output Control Enables (OUTCTL5-0)-Bits 13-8
343
Output Control Bits (OUT5-0)-Bits 5-0
343
PWM Counter Register (PMCNT)
343
Software Output Control
343
PWM Counter Modulo Register (PWMCM)
344
PWM Value Registers (PWMVAL0-5)
344
PWM Outputs
345
PWM Deadtime Register (PMDEADTM)
345
PWM Disable Mapping Registers (PMDISMAP1-2)
345
PWM Configure Register (PMCFG)
346
Reserved Bits-15-13, 11, and 7
346
Edge-Aligned or Center-Aligned Pwms (EDG)-Bit 12
346
Independent or Complimentary Pair Operation (INDEP)-Bits
347
Write Protect Bit (WP)-Bit 0
347
Enable Hardware Acceleration (ENHA) Bit-Bit15
348
Reserved Bits-Bits 14, 7-6, and 3
348
Value Register Load Mode (VLMODE[1:0])-Bits 5-4
348
Swap 5-6-Bit 2
348
Swap 3-2-Bit 1
348
PWM Port Register (PMPORT)
349
Channel Swapping
349
Serial Communications Interface (SCI)
351
Introduction
353
Features
353
Block Diagram
354
External Pin Descriptions
354
TXD Pin
354
RXD Pin
354
SCI Block Diagram
354
Register Summary
355
Definition of Terms
355
Functional Description
355
Data Frame Format
355
SCI Data Frame Formats
356
Example 8-Bit Data Frame Formats
356
Example 9-Bit Data Frame Format
356
Baud Rate Generation
357
Example Baud Rates (Module Clock = 40Mhz)
357
Block Diagram
358
Character Length
358
Character Transmission
358
Break Characters
360
Preambles
360
Receiver
361
Character Length
361
Character Reception
361
SCI Receiver Block Diagram
361
Data Sampling
362
Receiver Data Sampling
362
Stop Bit Recovery
364
Framing Errors
367
Baud Rate Tolerance
367
Slow Data Tolerance
368
Fast Data Tolerance
369
Receiver Wake-Up
370
Single-Wire Operation
371
Loop Operation
371
Register Descriptions
372
SCI Baud Rate Register (SCIBR)
372
Reserved Bits-Bits 15-13
372
SCI Baud Rate (SBR)-Bits 12-0
372
SCI Control Register (SCICR)
372
Loop Functions
373
Send Break Bit (SBK)-Bit 0
376
SCI Status Register (SCISR)
376
Transmit Data Register Empty Flag (TDRE)-Bit 15
376
Transmitter Idle Flag (TIDLE)-Bit 14
376
Receive Data Register Full Flag (RDRF)-Bit 13
376
Receiver Idle Line Flag (RIDLE)-Bit 12
377
Noise Flag (NF)-Bit 10
377
Framing Error Flag (FE)-Bit 9
377
Parity Error Flag (PF)-Bit 8
378
Receiver Active Flag (RAF)-Bit 0
378
SCI Data Register (SCIDR)
378
Reserved Bits-Bits 15-9
378
Receive Data-Bits 8-0
378
Transmit Data-Bits 8-0
378
Low-Power Options
379
Run Mode
379
Wait Mode
379
Stop Mode
379
Interrupt Operation
380
Interrupt Sources
380
Transmitter Interrupts
380
Receiver Interrupts
380
Recovery from Wait Mode
380
SCI Interrupt Sources
380
Serial Peripheral Interface (SPI)
381
Introduction
383
Features
383
Block Diagram
384
Pin Descriptions
384
MISO (Master In/Slave Out)
384
MOSI (Master Out/Slave In)
385
SCLK (Serial Clock)
385
SS (Slave Select)
385
CPHA / SS Timing
385
Register Summary
386
Internal I/O Signals
386
SPI IO Configuration
386
SPI Input Signals
386
External I/O Signals
387
SPI Output Signals
387
Functional Description
388
Operating Modes
388
Master Mode
388
Full-Duplex Master-Slave Connections
388
Slave Mode
389
Transmission Formats
390
Data Transmission Length
390
Data Shift Ordering
390
Clock Phase and Polarity Controls
390
Transmission Format When CPHA = 0
391
Transmission Format When CPHA = 1
392
CPHA / SS Timing
392
Transmission Initiation Latency
393
Transmission Data
394
Transmission Start Delay (Master)
395
Error Conditions
396
Overflow Error
396
SPRF / SPTE DSP Interrupt Timing
396
Missed Read of Overflow Condition
397
Mode Fault Error
398
Clearing SPI Receiver Full Bit When Overflow Bit
398
Interrupt Is Not Enabled
398
Interrupts
400
Resetting the SPI
401
SPI Interrupt Request Generation
401
Register Definitions
402
SPI Status and Control Register (SPSCR)
402
SPI Module Address Map
402
Reserved Bit
403
Data Shift Order Bit (DSO)-Bit 14
403
Error Interrupt Enable Bit (ERRIE)-Bit 12
403
Overflow Bit (OVRF)-Bit 11
404
Mode Fault Bit (MODF)-Bit 10
404
SPI Transmitter Empty Bit (SPTE)-Bit 9
404
Mode Fault Enable Bit (MODFEN)-Bit 8
404
SPI Baud Rate Select Bits (SPR1 and SPR0)-Bits 7- 6
405
SPI Receiver Interrupt Enable Bit (SPRIE)-Bit 5
405
SPI Master Bit (SPMSTR) - Bit 4
405
Clock Polarity Bit (CPOL)-Bit 3
405
SPI Master Baud Rate Selection
405
Clock Phase Bit (CPHA)-Bit 2
406
SPI Enable (SPE)-Bit 1
406
SPI Transmit Interrupt Enable (SPTIE)-Bit 0
406
SPI Data Size Register (SPDSR)
406
SPI Data Receive Register (SPDRR)
407
DS3-DS0-Transmission Data Size
407
SPI Data Transmit Register (SPDTR)
408
Quad Timer Module
409
Introduction
411
Features
412
Pin Descriptions
412
Counter/Timer Block Diagram
412
Register Summary
413
Functional Description
413
Counting Options
413
External Inputs
414
OFLAG Output Signal
414
Master Signal
414
Counting Mode Definitions
414
Stop Mode
414
Count Mode
415
Edge-Count Mode
415
Gated-Count Mode
415
Timing Diagram
415
Signed-Count Mode
416
Triggered-Count Mode
416
One-Shot Mode
416
Cascade-Count Mode
416
Pulse-Output Mode
417
Fixed-Frequency PWM Mode
417
Variable-Frequency PWM Mode
417
Usage of Compare Registers
418
Usage of Capture Register
418
Register Definitions
418
Control Registers (CTRL)
419
Count Mode-Bits 15-13
419
Primary Count Source-Bits 12-9
420
Secondary Count Source-Bits 8-7
421
Count Once (ONCE)-Bit 6
421
Count Length (LENGTH)-Bit 5
421
Count Direction (DIR)-Bit 4
421
Output Mode-Bits 2-0
422
Status and Control Registers (SCR)
422
Timer Compare Flag (TCF)-Bit
423
Timer Compare Flag Interrupt Enable (TCFIE)-Bit 14
423
Timer Overflow Flag (TOF)-Bit 13
423
Timer Overflow Flag Interrupt Enable (TOFIE)-Bit 12
423
Input Edge Flag (IEF)-Bit 11
423
Capture Register Operation
424
Output Enable (OEN)-Bit 0
425
Compare Register #1 (CMP1)
425
Compare Register #2 (CMP2)
426
Capture Register (CAP)
426
Load Register (LOAD)
427
Hold Register (HOLD)
428
Counter Register (CNTR)
428
Timer Group A, B, C, and D Functionality
429
Timer Group a (DSP56F803, DSP56F805, and DSP56F807 Only)
429
Timer Group B (DSP56F805 and DSP56F807 Only)
430
Timer Group C
430
DSP56F805 and DSP56F807 Only
430
DSP56F801, DSP56F803, DSP56F805, and DSP56F807
430
Timer Group D
431
Dsp56F801
431
DSP56F805 and DSP56F807
431
General Input Behavior
431
On-Chip Clock Synthesis (OCCS)
433
Introduction
435
Features
435
Pin Descriptions
435
Oscillator Inputs (XTAL, EXTAL)
435
External Crystal Design Considerations
435
Crystal Oscillator
435
External Clock Source
436
External Crystal Oscillator Circuit
436
Connecting an External Clock Signal Using XTAL
436
Register Summary
437
Connecting an External Clock Signal Using EXTAL
437
External Clock Timing
437
External Clock Operation Timing Requirements
437
Functional Description
438
Reference Clock Sources
438
OCCS Block Diagram
439
Timing
440
Changing Clock Sources
440
Register Definitions
441
PLL Control Register (PLLCR)
441
PLL Interrupt Enable 1 (PLLIE1[1:0])-Bits 15-14
441
Charge Pump Tri-State (CHPMPTRI)-Bit 6
442
Reserved Bit-Bit 5
442
PLL Power down (PLLPD)-Bit 4
442
Reserved Bit-Bit-3
442
Prescaler Clock Select (PRECS)-Bit 2
442
ZCLOCK Source (ZSRC[1:0])-Bits 1-0
443
PLL Divide-By Register (PLLDB)
443
Reserved Bits-Bit 7
443
Loss of Reference Timer Period (LORTP[3:0])-Bits 15-12
443
PLL Clock out Divide (PLLCOD[1:0])-Bits 11-10
443
PLL Clock in Divide (PLLCID[1:0])-Bits 9-8
444
PLL Divide-By (PLLDB[6:0])-Bits 6-0
444
PLL Status Register (PLLSR)
444
PLL Loss of Lock Interrupt 1 (LOLI1)-Bit 15
445
PLL Loss of Lock Interrupt 0 (LOLI0)-Bit 14
445
Loss of Clock (LOCI)-Bit 13
445
Reserved Bits-Bits 12-7 and 3
445
Loss of Lock 1 (LCK1)-Bit 6
445
PLL Power down (PLLPDN)-Bit 4
445
Prescaler Clock Status Source Register (PRECSS)-Bit 2
445
ZCLOCK Source (ZSRC[1:0])-Bit 1
446
Test Register (TESTR)
446
Test PLL Clock (TFDBK)-Bit 6
446
Test Feedback Clock (TFDBK)-Bit 5
447
Test Reference Frequency Clock (TFREF)-Bit 4
447
Force Loss of Clock (FLOCI)-Bit 3
447
Force Loss of Lock 1 (FLOLI1)-Bit 2
447
Force Loss of Lock 0 (FLOLI0)-Bit 1
447
Test Mode (TM)-Bit 0
447
CLKO Select Register (CLKOSR)
448
Reserved Bits-Bits 15-5
448
CLKO Select (CLKOSEL)-Bits 4-0
448
Internal Oscillator Control Register (IOSCTL)
449
DSP56F801 Clock Switch over Procedure
449
Disabling EXTAL and XTAL Pull up Resistors
449
External Crystal Oscillator Signal Generation
450
TRIM[7:0] - Internal Relaxation Oscillator TRIM Bits
450
Clock Operation in the Power-Down Modes
450
Relationship of Ipbus Clock and ZCLK
451
PLL Recommended Range of Operation
452
On-Chip Clock States
452
PLL Lock Time Specification
453
Lock Time Definition
453
Recommended Design Regions of OCCS PLL Operation
453
Parametric Influences on Reaction Time
454
PLL Frequency Lock Detector Block
454
Reset, Low Voltage, Stop and Wait Operations
455

Motorola DSP56F801 Hardware User Manual

Motorola DSP56F801 Hardware User Manual (56 pages)

Evaluation Module

Brand: Motorola | Category: Controller | Size: 0 MB

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