Table of Contents
Advertisement
Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
10.3.1.2
TCCR Transmit Prescaler Range (TPSR) - Bit 8
The TPSR bit controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit clock is
desired. When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed
divide-by-eight prescaler is operational (see Figure 10-3). The maximum internally generated
bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2
x 8 x 256)=Fosc/4096.
Note:
Do not use the combination TPSR=1 and TPM7-TPM0=$00, which causes
synchronization problems when using the internal DSP clock as source (TCKD=1
or THCKD=1).
10.3.1.3
TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 9–13
The TDC4–TDC0 bits control the divide ratio for the programmable frame rate dividers used
to generate the transmitter frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one.
The divide ratio may range from 2 to 32 (TDC[4:0]=00001 to 11111) for network mode. A
divide ratio of one (TDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from
1 to 32 (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1
(TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync
(TFSL=1) must be used in this case.
The ESAI frame sync generator functional diagram is shown in Figure 10-4.
10-12
DSP56367
MOTOROLA
Advertisement
Table of Contents
