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preamble generator are shown in Table 12-4. The preamble bits are already in the biphase
mark format.
There is no programmable control for the preamble selection. The first subframe to be
transmitted (immediately after the DAX is enabled) is the beginning of a block, and therefore
it has a "Z" preamble. This is followed by the second subframe, which has an "Y" preamble.
After that, "X" and "Y" preambles are transmitted alternately until the end of the block
transfer (192 frames transmitted). See Figure 12-4 for an illustration of the preamble
sequence.
DAX
Enabled
Here
Z
Y
12.5.11 DAX CLOCK MULTIPLEXER
The DAX clock multiplexer selects one of the clock sources and generates the biphase clock
(128 × Fs) and shift clock (64 × Fs). The clock source can be selected from the following
options (see also Section 12.5.6.4, "DAX Clock Input Select (XCS[1:0])—Bits 3–4").
The internal DSP core clock—assumes 1024 × Fs
•
DAX clock input pin (ACI)—512 × Fs
•
DAX clock input pin (ACI)—384 × Fs
•
DAX clock input pin (ACI)—256 × Fs
•
MOTOROLA
Table 12-4 Preamble Bit Patterns
Preamble
Bit Pattern
X
00011101
Y
00011011
Z
00010111
X
Y
X
Y
First Block (384 subframes)
Figure 12-4 Preamble sequence
DSP56367
Digital Audio Transmitter
DAX Internal Architecture
Channel
A
B
A (first in block)
X
Y
Z
Y
X
Second Block
Y
AA0609k
12-11
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