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Port D, 2-20, 7-2
Power, 2-3
power, 2-1, 2-1
power consumption benchmark test, E-1, F-1
power consumption design considerations, 4-4
Prescaler Counter, 13-5
Prescaler Counter Value bits (PC0-PC20), 13-6
Prescaler Load Value bits (PL0-PL20), 13-5
Prescaler Source bits (PL21-PL22), 13-5
Program Address Bus (PAB), 1-9
Program Address Generator (PAG), 1-7
Program Control Unit (PCU), 1-7
Program Counter register (PC), 1-8
Program Data Bus (PDB), 1-8
Program Decode Controller (PDC), 1-7
Program Interrupt Controller (PIC), 1-7
Program Memory Expansion Bus, 1-8
Programming Model
SHI—DSP Side, 9-6
SHI—Host Side, 9-5
R
recovery from Stop state using IRQA, 3-15, 3-16
reserved bits
in TCSR register
bits 3, 10, 14, 16–19, 22, 23, 13-12
in TPCR, 13-6
in TPLR, 13-6
RESET, 2-9
Reset timing, 3-9, 3-13
reverse-carry adder, 1-7
S
SC register, 1-8
Serial Host Interface, 2-1, 2-1, 2-13
Serial Host Interface (SHI), 1-14, 9-1
Serial Host Interface—See Section 5
Serial Peripheral Interface Bus, 1-14, 9-1
SHI, 1-14, 2-1, 2-1, 2-13, 9-1
Block Diagram, 9-3
Clock Control Register—DSP Side, 9-9
Clock Generator, 9-4, 9-4, 9-4
Control/Status Register—DSP Side, 9-13
Data Size, 9-13
Exception Priorities, 9-7
HCKR
Clock Phase and Polarity Controls, 9-10
Divider Modulus Select, 9-11
Prescaler Rate Select, 9-11
HCKR Filter Mode, 9-12
HCSR
Bus Error Interrupt Enable, 9-16
FIFO Enable Control, 9-14
Index-4
Index
Host Request Enable, 9-15
Idle, 9-15
Master Mode, 9-14
Serial Host Interface I
Serial Host Interface Mode, 9-13
SHI Enable, 9-13
Host Receive Data FIFO—DSP Side, 9-8
Host Transmit Data Register—DSP Side, 9-8
HREQ
Function In SHI Slave Modes, 9-15
HSAR
2
I
C Slave Address, 9-9
Slave Address Register, 9-9
I/O Shift Register, 9-8
Input/Output Shift Register—Host Side, 9-7
Internal Architecture, 9-2, 9-2
Internal Interrupt Priorities, 9-7
Interrupt Vectors, 9-7
Introduction, 9-1
Operation During Stop, 9-29
Programming Considerations, 9-22
Programming Model, 9-4
Programming Model—DSP Side, 9-6
Programming Model—Host Side, 9-5
Slave Address Register—DSP Side, 9-9
SHI Noise Reduction Filter Mode, 9-12
signal groupings, 2-1
signals, 2-1
Size register (SZ), 1-8
SP, 1-8
SPI, 1-14, 9-1
HCSR
Bus Error, 9-18
Host Busy, 9-18
Host Receive FIFO Full, 9-18
Host Receive FIFO Not Empty, 9-18
Host Receive Overrun Error, 9-18
Host Transmit Data Empty, 9-17
Host Transmit Underrun Error, 9-17
Receive Interrupt Enable, 9-16, 9-16
Master Mode, 9-23
Slave Mode, 9-22
SPI Data-To-Clock Timing, 9-10
SPI Data-To-Clock Timing Diagram, 9-10
SPI Mode, 9-1
SR register, 1-8
SRAM
interfacing, 1-11
read access, 3-20
read and write accesses, 3-17
write access, 3-21
SS, 1-8
Stack Counter register (SC), 1-8
Stack Pointer (SP), 1-8
2
C/SPI Selection, 9-13
MOTOROLA
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