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12.5
DAX INTERNAL ARCHITECTURE
Hardware components shown in Figure 12-1 are described in the following sections. The
DAX programming model is illustrated in Figure 12-2.
XCTR - Control Register - X:$FFFFD0
23
22
21
20
19
18
XNADR - Non-Audio Data Register - X:$FFFFD1
23
22
21
20
19
18
XADRA - Audio Data Register A - X:$FFFFD2 and XADRB - Audio Data Register B -X:$FFFFD3
23
XSTR - Status Register - X:$FFFFD4
23
22
21
20
19
18
Reserved bit
12.5.1
DAX AUDIO DATA REGISTER (XADR)
XADR is a 24-bit write-only register. One frame of audio data, which is to be transmitted in
the next frame slot, is transferred to this register. Successive write accesses to this register will
store channel A and channel B alternately in XADBUFA and in XADBUFB respectively.
When XADR and XADBUFA are empty, XADE bit in the XSTR is set, and, if the audio data
register empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core.
When channel B is transferred to XADR, the XADE bit in the XSTR is cleared. XADR can
also be accessed by DMA. When XADR and XADBUFA are empty, the DAX sends a DMA
request to the core. The DMA first transfers non-audio data bits to XNADR (optional), then
transfers channel A and channel B to XADR. The XADR can be accessed with two different
successive addresses. This feature supports sending non-audio data bits, channel A and
channel B to the DAX in three successive DMA transfers.
MOTOROLA
17
16
15
14
13
12
11
17
16
15
14
13
12
XCB
XUB
XVB
XCA
XUA
17
16
15
14
13
12
Figure 12-2 DAX Programming Model
DSP56367
Digital Audio Transmitter
DAX Internal Architecture
10
9
8
7
6
5
XSB
11
10
9
8
7
6
XVA
11
10
9
8
7
6
4
3
2
1
0
XCS1
XCS0
XBIE
XUIE
XDIE
5
4
3
2
1
0
0
5
4
3
2
1
0
XBLK
XAUR
XADE
12-5
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