Watchdog Modes - Motorola DSP56367 User Manual

Timer/ Event Counter
Timer Modes of Operation
The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF − TLR + 1). For a 50%
duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1) / 2.
Note: The value in TCPR must be greater than the value in TLR.
13.4.4

WATCHDOG MODES

13.4.4.1 Watchdog Pulse (Mode 9)
Bit Settings
TC3 TC2 TC1
1 0 0
In this mode, the timer generates an interrupt at a preset rate. Timer 0 also generates pulse on
TIO0. The signal period is equal to the period of one timer clock.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is
loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock
received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler
clock output. Each subsequent timer clock increments the counter.
When the counter matches the value of the TCPR, the TCF bit in the TCSR is set and a
compare interrupt is generated if the TCIE bit is also set.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the
count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each
subsequent timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated. Timer 0 also generates an output pulse on the TIO0 signal with a pulse width equal
to the timer clock period. The pulse polarity is determined by the value of the INV bit. If the
INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse polarity
is low (logical 0).
The counter contents can be read at any time by reading the TCR.
The counter is reloaded whenever the TLR is written with a new value while the TE bit is set.
13-22
TC0 Mode Name
1 9 Pulse
DSP56367
Mode Characteristics
Kind TIO0
Watchdog Output
Clock
Internal
MOTOROLA