Interrupt And Mode Control - Motorola DSP56367 User Manual

Signal/Connection Descriptions

Interrupt and Mode Control

Table 2-7 External Bus Control Signals (Continued)
Signal
Type
Name
BB Input/
Output
2.6 INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip's operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Signal Name Type
MODA/IRQA Input
MODB/IRQB Input
2-8
State
during
Reset
Input Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the bus is
active. Only after BB is deasserted can the pending bus master become the bus master
(and then assert the signal again). The bus master may keep BB asserted after ceasing bus
activity regardless of whether BR is asserted or deasserted. This is called "bus parking"
and allows the current bus master to reuse the bus without rearbitration until another
device requires the bus. The deassertion of BB is done by an "active pull-up" method (i.e.,
BB is driven high and then released and held high by an external pull-up resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR
register must be set.
BB requires an external pull-up resistor.
Table 2-8 Interrupt and Mode Control
State
during
Reset
Input Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into the OMR when the RESET signal is deasserted. If the processor is in the
stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the
stop state.
This input is 3.3V tolerant.
Input Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is deasserted.
This input is 3.3V tolerant.
DSP56367
Signal Description
Signal Description
MOTOROLA