Motorola DSP56367 User Manual page 472

24-bit digital signal processor
Table of Contents

Advertisement

RLIE
Description
0
Receive Last Slot Interrupt disabled
1
Receive Last Slot interrupt enabled
RIE
Description
0
Receive Interrupt disabled
1
Receive interrupt enabled
REDIE
0
Receive Even Slot Data Interrupt disabled
1
Receive Even Slot Data Interrupt enabled
REIE
0
Receive Exception Interrupt disabled
1
Receive Exception Interrupt enabled
RPR
0
Receiver Normal Operation
1
Receiver Personal Reset
RFSR
0
1
23
22
21
20
19
18
17
16
RLIE
RIE
REDIE
REIE
RFSR
RPR
Rsvd
Rsvd
RCR_1 - ESAI_1 Receive Control Register
Y: $FFFF97 Reset: $000000
Description
Description
Description
Description
Word-length frame sync synchronous to
beginning of data word first slot
Word-length frame sync 1 clock before
beginning of data word first slot
15
14
13
12
11
RFSL
RSWS4 RSWS3 RSWS2 RSWS1 RSWS0
RFSL
Description
0
Word length frame sync
1
1-bit clock period frame sync
RSWS [0:4]
Description
Defines slot and data word length
RMOD1 RMOD0
Network Mode
0
0
Normal mode
0
1
Network mode
1
0
Reserved
1
1
AC97
RWA
Description
0
Data left aligned
1
Data right aligned
RSHFD
0
1
RE [0:3]
0
1
10
9
8
7
6
5
RMOD0
RWA
RSHFD
Rsvd
RMOD1
ESAI_1
Description
Data shifted in MSB first
Data shifted in LSB first
Description
Receiver disabled
Receiver enabled
4
3
2
1
0
Rsvd
RE3
RE2
RE1
RE0

Advertisement

Table of Contents
loading

Table of Contents