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Specifications
Internal Clocks
3.6
INTERNAL CLOCKS
Characteristics
Internal operation frequency with PLL
enabled
Internal operation frequency with PLL
disabled
Internal clock high period
•
With PLL disabled
•
With PLL enabled and
MF ≤ 4
•
With PLL enabled and
MF > 4
Internal clock low period
•
With PLL disabled
•
With PLL enabled and
MF ≤ 4
•
With PLL enabled and
MF > 4
Internal clock cycle time with PLL
enabled
Internal clock cycle time with PLL
disabled
Instruction cycle time
Note:
1.
DF = Division Factor
Ef = External frequency
ET
= External clock cycle
C
MF = Multiplication Factor
PDF = Predivision Factor
T
= internal clock cycle
C
2.
Refer to the
3-6
Table 3-4 Internal Clocks
Symbol
f
f
T
H
0.49 × ET
PDF × DF/MF
0.47 × ET
PDF × DF/MF
T
L
0.49 × ET
PDF × DF/MF
0.47 × ET
PDF × DF/MF
T
C
T
C
I
CYC
DSP56300 Family Manual
DSP56367
Expression
Min
Typ
(Ef × MF)/
—
(PDF × DF)
—
Ef/2
—
ET
C
×
—
C
×
—
C
—
ET
C
×
—
C
×
—
C
× PDF ×
—
ET
C
DF/MF
2 × ET
—
—
T
C
for a detailed discussion of the PLL.
1, 2
Max
—
—
—
0.51 × ET
×
C
PDF × DF/MF
0.53 × ET
×
C
PDF × DF/MF
—
0.51 × ET
×
C
PDF × DF/MF
0.53 × ET
×
C
PDF × DF/MF
—
—
C
—
MOTOROLA
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