Motorola DSP56367 User Manual page 107

24-bit digital signal processor
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Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
No.
Characteristics
186
CAS assertion to data not valid (write)
187
RAS assertion to data not valid (write)
188
WR assertion to CAS assertion
189
CAS assertion to RAS assertion (refresh)
190
RAS deassertion to CAS assertion (refresh)
191
RD assertion to RAS deassertion
192
RD assertion to data valid
193
RD deassertion to data not valid
194
WR assertion to data active
195
WR deassertion to data high impedance
Note:
1.
The number of wait states for out-of-page access is specified in the DCR.
2.
The refresh period is specified in the DCR.
3.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is
t
and not t
OFF
4.
Either t
RCH
MOTOROLA
3
Symbol
t
t
t
t
t
3
.
GZ
or t
must be satisfied for read cycles.
RRH
DSP56367
External Memory Expansion Port (Port A)
Expression
6.25 × T
− 4.0
t
DH
C
9.75 × T
− 4.0
DHR
C
9.5 × T
− 4.3
WCS
C
1.5 × T
− 4.0
CSR
C
4.75 × T
− 4.0
RPC
C
15.5 × T
− 4.0
ROH
C
14 × T
− 5.7
t
GA
C
t
GZ
0.75 × T
− 0.3
C
0.25 × T
C
Specifications
Uni
Min
Max
t
48.1
ns
77.2
ns
74.9
ns
8.5
ns
35.6
ns
125.2
ns
111.0
ns
0.0
ns
5.9
ns
2.1
ns
3-41

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