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Serial Host Interface
Serial Host Interface Programming Model
9.5.5.1
Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
The Clock Phase (CPHA) bit controls the relationship between the data on the
master-in-slave-out (MISO) and master-out-slave-in (MOSI) pins and the clock produced or
received at the SCK pin. The CPOL bit determines the clock polarity (1 = active-high, 0 =
active-low).
The clock phase and polarity should be identical for both the master and slave SPI devices.
CPHA and CPOL are functional only when the SHI operates in the SPI mode, and are ignored
2
in the I
C mode. The CPHA bit is set and the CPOL bit is cleared during hardware reset and
software reset.
The programmer may select any of four combinations of serial clock (SCK) phase and
polarity when operating in the SPI mode (See Figure 9-6).
SS
SCK
(CPOL = 0, CPHA = 0)
SCK
(CPOL = 0, CPHA = 1)
SCK
(CPOL = 1, CPHA = 0)
SCK
(CPOL = 1, CPHA = 1)
MISO/
MOSI
Figure 9-6 SPI Data-To-Clock Timing Diagram
If CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device
whenever data is not being transferred. If the CPOL bit is set, it produces a high value at the
SCK pin of the master device whenever data is not being transferred.
CPHA is used with the CPOL bit to select the desired clock-to-data relationship. The CPHA
bit, in general, selects the clock edge that captures data and allows it to change states. It has its
greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock
transition before the data capture edge.
9-10
MSB
6
5
4
Internal Strobe for Data Capture
DSP56367
3
2
1
LSB
MOTOROLA
AA0421
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