Table of Contents
Advertisement
DSP56367 Overview
DSP56367 Audio Processor Architecture
– 40Kx24 Bit Program ROM.
– 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM
may be used as Instruction Cache or for Program ROM patching.
– 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched
to Program RAM resulting in up to 10Kx24 Bit of Program RAM.
•
Off-chip memory expansion
– External Memory Expansion Port.
– Off-chip expansion up to two 16M x 24-bit word of Data memory.
– Off-chip expansion up to 16M x 24-bit word of Program memory.
– Simultaneous glueless interface to SRAM and DRAM.
•
Peripheral modules
– Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or
2
slave. I
S, Sony, AC97, network and other programmable protocols.
– Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters,
master or slave. I
The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT
support HCKR and HCKT (high frequency clocks)
– Serial Host Interface (SHI): SPI and I
10-word receive FIFO, support for 8, 16 and 24-bit words.
– Byte-wide parallel Host Interface (HDI08) with DMA support.
– Triple Timer module (TEC).
– Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the
SPDIF, IEC958, CP-340 and AES/EBU digital audio formats.
– Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
•
144-pin plastic LQFP package.
1.3
DSP56367 AUDIO PROCESSOR ARCHITECTURE
This section defines the DSP56367 audio processor architecture. The audio processor is
composed of the following units:
•
The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program
Controller, Instruction-Cache Controller, DMA Controller, PLL-based clock
oscillator, Memory Module Interface, Peripheral Module Interface and the On-Chip
1-4
2
S, Sony, AC97, network and other programmable protocols
2
C protocols, multi master capability,
DSP56367
MOTOROLA
Advertisement
Table of Contents
