Frame Sync For Receiver (Fsr) - Motorola DSP56367 User Manual

or by all the enabled transmitters and receivers in the synchronous mode (SYN=1) (see
Table 10-2).
THCKD TFSD
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT
function is not being used.
Note: Although the external ESAI serial clock can be independent of and asynchronous
to the DSP system clock, the DSP clock frequency must be at least three times the
external ESAI serial clock frequency and each ESAI serial clock phase must
exceed the minimum of 1.5 DSP clock periods.
10.2.9

FRAME SYNC FOR RECEIVER (FSR)

FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface.
The direction of this pin is determined by the RFSD bit in RCR register. In the asynchronous
mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). For
further information on pin mode and definition, see Table 10-8 and on receiver clock signals
see Table 10-1.
When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in
the RCCR register. When configured as the output flag OF1, this pin reflects the value of the
OF1 bit in the SAICR register, and the data in the OF1 bit shows up at the pin synchronized to
the frame sync being used by the transmitter and receiver sections. When configured as the
MOTOROLA
Table 10-2 Transmitter Clock Sources
Transmitter
TCKD
Bit Clock Source
0 SCKT
1 HCKT
0 SCKT
1 HCKT
0 SCKT
1 INT
0 SCKT
1 INT
DSP56367
Enhanced Serial Audio Interface (ESAI)
ESAI Data and Control Pins
OUTPUTS
FST
FST
HCKT
HCKT
HCKT FST
HCKT FST
SCKT
SCKT
SCKT
SCKT
10-7