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Serial Host Interface
Characteristics Of The I
•
Stop data transfer—The stop event is defined as a change in the state of the data line,
from low to high, while the clock is high (see Figure 9-8).
•
Data valid—The state of the data line represents valid data when, after a start event,
the data line is stable for the duration of the high period of the clock signal. The data
on the line may be changed during the low period of the clock signal. There is one
clock pulse per bit of data.
SDA
SCL
S
Start Event
Each 8-bit word is followed by one acknowledge bit. This acknowledge bit is a high level put
on the bus by the transmitter when the master device generates an extra acknowledge-related
clock pulse. A slave receiver that is addressed must generate an acknowledge after each byte
is received. Also, a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The acknowledging device must pull
down the SDA line during the acknowledge clock pulse so that the SDA line is stable low
during the high period of the acknowledge-related clock pulse (see Figure 9-9).
Start
Event
SCL From
Master Device
Data Output
by Transmitter
S
Data Output
by Receiver
Figure 9-9 Acknowledgment on the I
9-20
2
C Bus
2
Figure 9-8 I
C Start and Stop Events
1
DSP56367
2
2
C Bus
P
Stop Event
AA0423
Clock Pulse For
Acknowledgment
8
9
AA0424
MOTOROLA
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