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Specifications
Phase Lock Loop (PLL) Characteristics
No.
Note:
1.
Measured at 50% of the input transition
2.
The maximum value for PLL enabled is given for minimum V
MF.
3.
The maximum value for PLL enabled is given for minimum VCO and maximum
DF.
4.
The indicated duty cycle is for the specified maximum frequency for which a part
is rated. The minimum clock high or low time required for correct operation,
however, remains the same at lower operating frequencies; therefore, when a lower
clock frequency is used, the signal symmetry may vary from the specified duty
cycle as long as the minimum high time and low time requirements are met.
3.8
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Characteristics
V
frequency when PLL enabled
CO
(MF × E
× 2/PDF)
f
PLL external capacitor (PCAP pin to V
@ MF ≤ 4
•
•
@ MF > 4
Note:
1.
C
is the value of the PLL capacitor (connected between the PCAP pin and V
PCAP
recommended value in pF for C
(MF x 680)-120, for MF ≤ 4, or
MF x 1100, for MF > 4.
3-8
Table 3-5 Clock Operation (Continued)
Characteristics
Table 3-6 PLL Characteristics
1)
) (C
CCP
PCAP
PCAP
DSP56367
Symbol
Min
30
(MF × 580) − 100
MF × 830
can be computed from one of the following equations:
Min
Max
and maximum
CO
Max
Unit
240
MHz
pF
(MF × 780) − 140
MF × 1470
). The
CCP
MOTOROLA
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