Host Data Register (Hdr) - Motorola DSP56367 User Manual

8.5.8

HOST DATA REGISTER (HDR)

The HDR register holds the data value of the corresponding bits of the HDI08 pins which are
configured as GPIO pins. The functionality of the Dxx bit depends on the corresponding
HDDR bit (DRxx). See Table 8-6.
Figure 8-10 Host Data Register (HDR) (X:$FFFFC9)
15 14 13 12
D15 D14 D13 D12
HDDR
DRxx
0 Read only bit. The value read is the binary value of the pin.
The corresponding pin is configured as an input.
1 Read/write bit. The value written is the value read. The
corresponding pin is configured as an output, and is driven
with the data written to Dxx.
a.Defined by the selected configuration
8.5.9 DSP-SIDE REGISTERS AFTER RESET
Table 8-7 shows the results of the four reset types on the bits in each of the HDI08 registers
accessible by the DSP core. The hardware reset (HW) is caused by the RESET signal. The
software reset (SW) is caused by executing the RESET instruction. The individual reset (IR)
MOTOROLA
11 10 9
D11 D10 D9
Table 8-6 HDR and HDDR Functionality
a
GPIO pin
DSP56367
HDI08 – DSP-Side Programmer's Model
8 7 6 5
D8 D7 D6 D5
HDR
Dxx
Read only bit. Does not contain significant data.
Read/write bit. The value written is the value read.
Host Interface (HDI08)
4 3 2 1
D4 D3 D2 D1
a
non-GPIO pin
8-17
0
D0