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Application
Central Processor
External Bus Disable
Stop Delay
Memory Switch Mode
Core-DMA Priority
CDP(1:0)
Core-DMA Priority
00
Core vs DMA Priority
01
DMA accesses > Core
10
DMA accesses = Core
11
DMA accesses < Core
Burst Mode Enable
TA Synchronize Select
Bus Release Timing
Asynchronous Bus Arbitration Enable
Address Priority Disable
Address Tracing Enable
Stack Extension Space Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
Memory Switch Mode
Patch Enable
23 22
21 20
19 18 17 16
WRP EOV EUN XYS
PEN
SEN
MSW1 MSW0
System Stack Control
Status Register (SCS)
Operating Mode Register (OMR)
MOTOROLA
MOD(D:A) Reset Vector
15 14 13 12 11 10
ABE
ATE APD
Extended Chip Operating
Mode Register (COM)
Read/Write Reset = $00030X
Figure D-2 Operating Mode Register (OMR)
DSP56367
Chip Operating Modes
See Core Configuration Section.
9
8
7
BRT TAS
BE
CDP1CDP0
MS
Programmer's Reference
Date:
Programmer:
Sheet 2 of 5
Description
6
5
4
3
2
1
SD
EBD
MD
MC MB
*
0
Chip Operating Mode
Register (COM)
= Reserved, Program as 0
*
0
MA
D-17
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