Tccr_1 Tx High Freq. Clock Divider (Tfp3-Tfp0) - Bits 14–17 - Motorola DSP56367 User Manual

Hardware and software reset clear all the bits of the TCCR_1 register.
11
Y:$FFFF96 TDC2 TDC1
23
THCKD TFSD
11.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14–17
Since the ESAI_1 does not have the transmitter high frequency clock pin, the TFP3–TFP0 bits
simply specify an additional division ratio in the clock divider chain. See Figure 11-4.
11.3.2.2 TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20
The ESAI_1 does not have the transmitter high frequency clock pin. It it recommended that
THCKP should be kept cleared.
11.3.2.3 TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23
The ESAI_1 does not have the transmitter high frequency clock pin. THCKD must be set for
proper ESAI_1 transmitter section operation.
THCKD
0
1
1
1
1
MOTOROLA
10 9 8 7
TDC0 TPSR TPM7
22 21 20 19
TCKD THCKP TFSP
Figure 11-3 TCCR_1 Register
Table 11-2 Transmitter Clock Sources
TFSD TCKD
X X
0 0
0 1
1 0
1 1
DSP56367
Enhanced Serial Audio Interface 1 (ESAI_1)
ESAI_1 Programming Model
6 5 4
TPM6 TPM5 TPM4
18 17 16
TCKP TFP3 TFP2
Transmitter
Bit Clock Source
Reserved
SCKT_1
INT
SCKT_1 FST_1
INT FST_1
3 2 1
TPM3 TPM2 TPM1 TPM0
15 14 13
TFP1 TFP0 TDC4 TDC3
OUTPUTS
SCKT_1
SCKT_1
11-7
0
12