Table of Contents
Advertisement
Host Interface (HDI08)
HDI08 – DSP-Side Programmer's Model
8.5.6.5
HPCR Host Request Enable (HREN) Bit 4
The HREN bit controls the host request signals. If HREN is set and the HDI08 is in the single
host request mode (HDRQ=0 in the ICR), HOREQ/HTRQ is configured as the host request
(HOREQ) output.
If HREN is set in the double host request mode (HDRQ=1 in the ICR), HOREQ/HTRQ is
configured as the host transmit request (HTRQ) output and HACK/HRRQ as the host receive
request (HRRQ) output.
If HREN is cleared, HOREQ/HTRQ and HACK/HRRQ are configured as GPIO pins
according to the value of HDDR and HDR registers.
8.5.6.6
HPCR Host Acknowledge Enable (HAEN) Bit 5
The HAEN bit controls the HACK signal. In the single host request mode (HDRQ=0 in the
ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as the host acknowledge
(HACK) input. If HAEN or HREN is cleared, HACK/HRRQ is configured as a GPIO pin
according to the value of HDDR and HDR registers. In the double host request mode
(HDRQ=1 in the ICR), HAEN is ignored.
8.5.6.7
HPCR Host Enable (HEN) Bit 6
If the HEN bit is set, the HDI08 operation is enabled as Host Interface. If cleared, the HDI08
is not active, and all the HDI08 pins are configured as GPIO pins according to the value of
HDDR and HDR registers.
8.5.6.8
HPCR Reserved Bit 7
This bit is reserved. It reads as zero and should be written with zero for future compatibility.
8.5.6.9
HPCR Host Request Open Drain (HROD) Bit 8
The HROD bit controls the output drive of the host request signals. In the single host request
mode (HDRQ=0 in ICR), if HROD is cleared and host requests are enabled (HREN=1 and
HEN=1 in HPCR), the HOREQ signal is always driven. If HROD is set and host requests are
enabled, the HOREQ signal is an open drain output.
In the double host request mode (HDRQ=1 in the ICR), if HROD is cleared and host requests
are enabled (HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are always
driven. If HROD is set and host requests are enabled, the HTRQ and HRRQ signals are open
drain outputs.
8.5.6.10
HPCR Host Data Strobe Polarity (HDSP) Bit 9
If the HDSP bit is cleared, the data strobe signals are configured as active low inputs, and data
is transferred when the data strobe is low. If HDSP is set, the data strobe signals are
configured as active high inputs, and data is transferred when the data strobe is high. The data
strobe signals are either HDS by itself or HRD and HWR together.
8-14
DSP56367
MOTOROLA
Advertisement
Table of Contents
