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Host Interface (HDI08)
HDI08 – DSP-Side Programmer's Model
8.5.3.2
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The HTIE bit is used to enable the host transmit data empty interrupt request. When the host
transmit data empty (HTDE) status bit in the HSR is set, a host transmit data interrupt request
occurs if HTIE is set. If HTIE is cleared, HTDE interrupts are disabled.
8.5.3.3
HCR Host Command Interrupt Enable (HCIE) Bit 2
The HCIE bit is used to enable the host command interrupt request. When the host command
pending (HCP) status bit in the HSR is set, a host command interrupt request occurs if HCIE
is set. If HCIE is cleared, HCP interrupts are disabled. The interrupt address is determined by
the host command vector register (CVR).
Note:
Host interrupt request priorities: If more than one interrupt request source is
asserted and enabled (e.g. HRDF=1, HCP=1, HRIE=1 and HCIE=1), the HDI08
generates interrupt requests according to the following table:
8.5.3.4
HCR Host Flags 2,3 (HF2,HF3) Bits 3-4
HF2 and HF3 bits are used as a general-purpose flags for DSP to host communication. HF2
and HF3 may be set or cleared by the DSP core. HF2 and HF3 are reflected in the interface
status register (ISR) on the host side such that if they are modified by the DSP software, the
host processor can read the modified values by reading the ISR.
These two flags are not designated for any specific purpose but are general-purpose flags.
They can be used individually or as encoded pairs in a simple DSP to host communication
protocol, implemented in both the DSP and the host processor software.
8.5.3.5
HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7
The HDM[2:0] bits are used to enable the HDI08 DMA mode operation. The HDI08 DMA
mode supports external DMA controller devices connected to the HDI08 on the Host side.
This mode should not be confused with the operation of the on-chip DMA controller.
With HDM[2:0] cleared, the HDI08 does not support DMA mode operation and the TREQ
and RREQ control bits are used for host processor interrupt control via the external HOREQ
output signal (or HRREQ and HTREQ output signals if HDREQ in the ICR is set). Also, in
the non-DMA mode, the HACK input signal is used for the MC68000 Family vectored
8-8
Table 8-4 HDI08 IRQ
Priority
Interrupt Source
Highest
Host Command (HCP=1)
Transmit Data (HTDE=1)
Lowest
Receive Data (HRDF=1)
DSP56367
MOTOROLA
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