Tplr Reserved Bit 23 - Motorola DSP56367 User Manual

Timer/ Event Counter
Timer/Event Counter Programming Model
The PS[1:0] bits are cleared by the hardware RESET signal or the software RESET
instruction.
Note: To ensure proper operation, change the PS[1:0] bits only when the prescaler
counter is disabled. Disable the prescaler counter by clearing the TE bit in the
TCSR of each of three timers.
PS1
0
0
1
1
13.3.2.3

TPLR Reserved Bit 23

This reserved bit is read as zero and should be written with zero for future compatibility.
13.3.3 TIMER PRESCALER COUNT REGISTER (TPCR)
The TPCR is a 24-bit read-only register that reflects the current value in the prescaler counter.
See Figure 13-5.
23 22 21
11 10 9
PC11 PC10 PC9
— reserved, read as 0, should be written with 0 for future compatibility
Figure 13-5 Timer Prescaler Count Register (TPCR)
13.3.3.1 TPCR Prescaler Counter Value PC[20:0] Bits 20–0
These 21 bits contain the current value of the prescaler counter.
13.3.3.2 TPCR Reserved Bits 23–21
These reserved bits are read as zero and should be written with zero for future compatibility.
13-6
Table 13-1 Prescaler Source Selection
PS0
0
1
0
1
19 18
20
PC20 PC19 PC18
8 7 6
PC8 PC7 PC6
DSP56367
PRESCALER CLOCK SOURCE
Internal CLK/2
TIO0
Reserved
Reserved
17 16 15
PC17 PC16 PC15
5 4 3
PC5 PC4 PC3
14 13 12
PC14 PC13 PC12
2 1 0
PC2 PC1 PC0
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