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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
2.5
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant port A signals: A0–A17, D0–D23,
AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.
2.5.1
EXTERNAL ADDRESS BUS
Signal Name
Type
A0–A17
Output
2.5.2
EXTERNAL DATA BUS
Signal Name
Type
D0–D23
Input/Output
2.5.3
EXTERNAL BUS CONTROL
Signal
Type
Name
AA0–AA2/
Output
RAS0–RAS
2
2-6
Table 2-5 External Address Bus Signals
State
during
Reset
Tri-stated
Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs that
specify the address for external program and data memory accesses. Otherwise, the
signals are tri-stated. To minimize power dissipation, A0–A17 do not change state
when external memory spaces are not being accessed.
Table 2-6 External Data Bus Signals
State during Reset
Tri-stated
Table 2-7 External Bus Control Signals
State
during
Reset
Tri-stated
Address Attribute or Row Address Strobe—When defined as AA, these signals can be
used as chip selects or additional address lines. When defined as RAS, these signals can
be used as RAS for DRAM interface. These signals are tri-statable outputs with
programmable polarity.
DSP56367
Signal Description
Signal Description
Data Bus—When the DSP is the bus master, D0–D23 are
active-high, bidirectional input/outputs that provide the bidirectional
data bus for external program and data memory accesses. Otherwise,
D0–D23 are tri-stated.
Signal Description
MOTOROLA
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