Host Side Registers After Reset - Motorola DSP56367 User Manual

8.6.7

HOST SIDE REGISTERS AFTER RESET

Table 8-15 shows the result of the four kinds of reset on bits in each of the HDI08 registers
seen by the host processor. The hardware reset (HW) is caused by asserting the RESET signal.
The software reset (SW) is caused by executing the RESET instruction. The individual reset
(IR) is caused by clearing the HEN bit in the HPCR register. The stop reset (ST) is caused by
executing the STOP instruction.
Table 8-15 Host Side Registers After Reset
Register Register
Name Data
ICR All Bits
CVR HC
HV[6:0]
ISR HREQ
HF3-HF2
TRDY
TXDE
RXDF
IVR IV[7:0]
RX RXH:RXM:RXL
TX TXH:TXM:TXL
Note: A long dash (—) denotes that the register value is not affected by the specified reset.
8.6.8 GENERAL PURPOSE INPUT/OUTPUT (GPIO)
When configured as general-purpose I/O, the HDI08 is viewed by the DSP core as
memory-mapped registers (see Section 8.5, "HDI08 – DSP-Side Programmer's Model") that
control up to 16 I/O pins. The software and hardware resets clear all DSP-side control
registers and configure the HDI08 as GPIO with all 16 signals disconnected. External
circuitry connected to the HDI08 may need external pull-up/pull-down resistors until the
signals are configured for operation. The registers cleared are the HPCR, HDDR and HDR.
Selection between GPIO and HDI08 is made by clearing HPCR bits 6 through 1 for GPIO or
setting these bits for HDI08 functionality. If the HDI08 is in GPIO mode, the HDDR
configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared
or as an output signal if the HDDR bit is set (see Section 8.5.7 and Section 8.5.8).
MOTOROLA
HDI08 – External Host Programmer's Model
HW SW
Reset Reset
0 0
0 0
$32 $32
0 0 1 if TREQ is set;
0 0
1 1
1 1
0 0
$0F $0F
empty empty
empty empty
DSP56367
Host Interface (HDI08)
Reset Type
IR
Reset
—
0
—
1 if TREQ is set;
0 otherwise
—
1
1
0
—
empty
empty
ST
Reset
—
0
—
0 otherwise
—
1
1
0
—
empty
empty
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