Host Receive Fifo Not Empty (Hrne)—Bit 17 - Motorola DSP56367 User Manual

Serial Host Interface
Serial Host Interface Programming Model
9.5.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit HRNE indicates that the Host Receive FIFO (HRX) contains at least
one data word. HRNE is set when the FIFO is not empty. HRNE is cleared when HRX is read
by the DSP (read instructions or DMA transfers), reducing the number of words in the FIFO
to zero. HRNE is cleared during hardware reset, software reset, SHI individual reset, and
during the stop state.
9.5.6.16 Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full.
HRFF is cleared when HRX is read by the DSP (read instructions or DMA transfers) and at
least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset,
SHI individual reset, and during the stop state.
9.5.6.17 Host Receive Overrun Error (HROE)—Bit 20
The read-only status bit HROE indicates, when set, that a data-receive overrun error has
occurred. Receive-overrun errors cannot occur when operating in the I
because the clock is suspended if the receive FIFO is full; nor can they occur in the I
mode when HCKFR is set.
HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to the
HRX FIFO and the FIFO is already full (HRFF is set). When a receive-overrun error occurs,
the shift register is not transferred to the FIFO. If a receive interrupt occurs with HROE set,
the receive-overrun interrupt vector is generated. If a receive interrupt occurs with HROE
cleared, the regular receive-data interrupt vector is generated.
HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is
cleared by hardware reset, software reset, SHI individual reset, and during the stop state.
9.5.6.18 Host Bus Error (HBER)—Bit 21
The read-only status bit HBER indicates, when set, that an SHI bus error occurred when
operating as a master (HMST set). In I
receive an acknowledge after a byte is transferred; then a stop event is generated and
transmission is suspended. In SPI mode, HBER is set if SS is asserted; then transmission is
suspended at the end of transmission of the current word. HBER is cleared only by hardware
reset, software reset, SHI individual reset, and during the stop state.
9.5.6.19 HCSR Host Busy (HBUSY)—Bit 22
The read-only status bit HBUSY indicates that the I
that the SHI itself is busy (when in the SPI mode). When operating in the I
is set after the SHI detects a start event and remains set until a stop event is detected. When
operating in the slave SPI mode, HBUSY is set while SS is asserted. When operating in the
master SPI mode, HBUSY is set if the HTX register is not empty or if the IOSR is not empty.
9-18
2
C mode, HBER is set if the transmitter does not
2
C bus is busy (when in the I
DSP56367
2
C master mode,
2
C slave
2
C mode) or
2
C mode, HBUSY
MOTOROLA