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4.2
ELECTRICAL DESIGN CONSIDERATIONS
Use the following list of recommendations to assure correct DSP operation:
•
Provide a low-impedance path from the board power supply to each V
DSP and from the board ground to each GND pin.
Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the
•
four sides of the package to connect the V
•
Ensure that capacitor leads and associated printed circuit traces that connect to the
chip V
and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.
CC
•
Use at least a four-layer PCB with two inner layers for V
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths should
be minimal. This recommendation particularly applies to the address and data buses as
well as the IRQA, IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the
order of 15 cm (6 inches) are recommended.
•
Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the V
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except
for the three pins with internal pull-up resistors (TMS, TDI, TCK).
•
Take special care to minimize noise levels on the V
•
If multiple DSP56367 devices are on the same board, check for cross-talk or excessive
spikes on the supplies due to synchronous operation of the devices.
MOTOROLA
CAUTION
This device contains circuitry protecting
against damage due to high static voltage
or electrical fields. However, normal
precautions should be taken to avoid
exceeding
maximum
Reliability of operation is enhanced if
unused inputs are tied to an appropriate
logic voltage level (e.g., either GND or
V
). The suggested value for a pullup or
CC
pulldown resistor is 10 k ohm.
DSP56367
Design Considerations
Electrical Design Considerations
voltage
ratings.
power source to GND.
CC
and GND.
CC
and GND circuits.
CC
and GND
CCP
pin on the
CC
pins.
P
4-3
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