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Timer/ Event Counter
Timer/Event Counter Architecture
GDB
24
TPLR
Timer Prescaler
Load Register
21-bit Prescaler
Counter
CLK/2
Figure 13-1 Timer/Event Counter Block Diagram
13.2.2
INDIVIDUAL TIMER BLOCK DIAGRAM
Figure 13-2 shows the structure of an individual timer module. The three timers are identical
in structure, but only timer 0 is externally accessible.
Each timer includes a 24-bit counter, a 24-bit read/write timer control and status register
(TCSR), a 24-bit read-only timer count register (TCR), a 24-bit write-only timer load register
(TLR), a 24-bit read/write timer compare register (TCPR), and logic for clock selection and
interrupt/DMA trigger generation.
The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR).
Timer modes are described in Section 13.4.
13-2
24
24
TPCR
Timer Prescaler
Count Register
TIO0
DSP56367
Timer 0
Timer 1
Timer 2
MOTOROLA
24
AA0673
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