Motorola DSP56367 User Manual page 521

Status Register (SR), 1-8
Stop state
recovery from, 3-15, 3-16
Stop timing, 3-9
supply voltage, 3-2
System Stack (SS), 1-8
SZ register, 1-8
T
TAP, 1-10
TC0–TC3 bits, 13-7
TCF, 13-12
TCIE bit, 13-7
TCPR, 13-13
TCR, 13-13
TCSR register, 13-7
bit 0—Timer Enable bit (TE), 13-7
bit 2—Timer Compare Interrupt Enable bit
(TCIE), 13-7
bits 4–7—Timer Control bits (TC0–TC3), 13-7
bit 13—Data Output bit (DO), 13-11
reserved bits—bits 3, 10, 14, 16–19, 22, 23, 13-12
TE bit, 13-7
Test Access Port (TAP), 1-10
Test Access Port timing diagram, 3-76
Test Clock (TCLK) input timing diagram, 3-75
thermal characteristics, 3-2
thermal design considerations, 4-1, 4-1
Timer, 2-1, 2-1, 2-21
event input restrictions, 3-73
timing, 3-73
timer
special cases, 13-24
Timer (GPIO), 7-2
Timer Compare Interrupt Enable bit (TCIE), 13-7
Timer Control bits (TC0–TC3), 13-7
Timer Control/Status Register (TCSR), 13-7
Timer Enable bit (TE), 13-7
timer mode
mode 0—GPIO, 13-14
mode 1—timer pulse, 13-15
mode 2—timer toggle, 13-16
mode 3—timer event counter, 13-17
mode 4—measurement input width, 13-18
mode 5—measurement input period, 13-19
mode 6—measurement capture, 13-20
mode 7—pulse width modulation, 13-21
mode 8—reserved, 13-22
mode 9—watchdog pulse, 13-22, 13-23
modes 11–15—reserved, 13-24
Timer module
architecture, 13-1
Timer Prescaler Count Register (TPCR), 13-6
Timer Prescaler Load Register (TPLR), 13-5
MOTOROLA
Index
Timing
Digital Audio Transmitter (DAX), 3-72
Enhanced Serial Audio Interface (ESAI), 3-68
General Purpose I/O (GPIO) Timing, 3-66
OnCE™ (On Chip Emulator) Timing, 3-66
Serial Host Interface (SHI) SPI Protocol Timing, 3-
55
Serial Host Interface (SHI) Timing, 3-55
timing
interrupt, 3-9
mode select, 3-9
Reset, 3-9
Stop, 3-9
TLR, 13-12
TOF, 13-11
TOIE, 13-7
TPCR register, 13-6
bits 0-20—Prescaler Counter Value bits (PC0-
PC20), 13-6
bit 21-23—reserved bits, 13-6
reserved bits—bits 21-23, 13-6
TPLR register, 13-5
bits 0-20—Prescaler Load Value bits (PL0-
PL20), 13-5
bits 21-22—Prescaler Source bits (PL0-PL20), 13-5
bit 23—reserved bit, 13-6
reserved bit—bit 23, 13-6
TQFP
pin list by number, 14-5
pin-out drawing (top), 14-1
TQFP package drawing, 14-8
Transmitter High Frequency Clock Divider, 10-14
TRM, 13-10
V
VBA register, 1-8
Vector Base Address register (VBA), 1-8
X
X Memory Address Bus (XAB), 1-9
X Memory Data Bus (XDB), 1-8
X Memory Expansion Bus, 1-8
XAB, 1-9
XDB, 1-8
Y
Y Memory Address Bus (YAB), 1-9
Y Memory Data Bus (YDB), 1-8
Y Memory Expansion Bus, 1-8
YAB, 1-9
YDB, 1-8
Index-5