Section 5 Memory Configuration - Motorola DSP56367 User Manual

SECTION 5
MEMORY CONFIGURATION
5.1 DATA AND PROGRAM MEMORY MAPS
The on-chip memory configuration of the DSP56367 is affected by the state of the CE (Cache
Enable), MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register, and by
the SC bit in the Status Register. The internal data and program memory configurations are
shown in Table 5-1. The address ranges for the internal memory are shown in Table 5-2 and
Table 5-3. The memory maps for each memory configuration are shown in Figure 5-1 to
Figure 5-16.
MOTOROLA DSP56367 5-1