Specifications
Serial Host Interface SPI Protocol Timing
Table 3-19 Serial Host Interface SPI Protocol Timing (Continued)
No.
Characteristics
146
SS assertion to first SCK edge
CPHA = 0
CPHA = 1
147
Last SCK edge to SS not asserted
148
Data input valid to SCK edge (data input
set-up time)
149
SCK last sampling edge to data input not
valid
150
SS assertion to data out active
151
SS deassertion to data high impedance
152
SCK edge to data out valid
(data out delay time)
153
SCK edge to data out not valid
(data out hold time)
154
SS assertion to data out valid
(CPHA = 0)
3-56
Filter
1
Mode
Mode
Slave
Bypassed
Narrow
Wide
Slave
Bypassed
Narrow
Wide
Slave
Bypassed
Narrow
Wide
Maste
Bypassed
r/Slav
Narrow
e
Wide
Maste
Bypassed
r/Slav
e
Narrow
Wide
Slave
2
Slave
Maste
Bypassed
r/Slav
e
Narrow
Wide
Maste
Bypassed
r/Slav
e
Narrow
Wide
Slave
DSP56367
Expression
3.5×T
+15
C
0
0
10
0
0
12
102
189
0
MAX{(20-T
), 0}
C
MAX{(40-T
), 0}
C
2.5×T
+10
C
2.5×T
+30
C
2.5×T
+50
C
—
2
—
9
2×T
+33
C
2×T
+123
C
2×T
+210
C
T
+5
C
T
+55
C
T
+106
C
—
T
+33
C
Min
Max
Unit
44.2
—
ns
0
—
ns
0
—
ns
10
—
ns
0
—
ns
0
—
ns
12
—
ns
102
—
ns
189
—
ns
0
—
ns
11.7
—
ns
31.7
—
ns
30.8
—
ns
50.8
—
ns
70.8
—
ns
2
—
ns
—
9
ns
—
49.7
ns
—
139.7
ns
—
226.7
ns
13.3
—
ns
63.3
—
ns
114.3
—
ns
—
41.3
ns
MOTOROLA