Rccr_1 Rx High Freq. Clock Divider (Rfp3-Rfp0) - Bits 14–17 - Motorola DSP56367 User Manual

11.3.4.1 RCCR_1 Rx High Freq. Clock Divider (RFP3-RFP0) - Bits 14–17
Since the ESAI_1 does not have the receiver high frequency clock pin, the RFP3–RFP0 bits
simply specify an additional division ratio in the clock divider chain. See Figure 11-4.
11.3.4.2 RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20
The ESAI_1 does not have the receiver high frequency clock pin. It it recommended that
RHCKP should be kept cleared.
11.3.4.3 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23
The ESAI_1 does not have the receiver high frequency clock pin. RHCKD must be set for
proper ESAI_1 receiver section operation.
Table 11-3 Receiver Clock Sources (asynchronous mode only)
RHCKD
0
1
1
1
1
11.3.5 ESAI_1 RECEIVE CONTROL REGISTER (RCR_1)
The read/write Receive Control Register (RCR_1) controls the ESAI_1 receiver section.
11
Y:$FFFF97 RSWS1 RSWS0 RMOD1 RMOD0 RWA
23
RLIE
Hardware and software reset clear all the bits in the RCR_1 register.
MOTOROLA
RFSD RCKD
X X
0 0
0 1
1 0
1 1
10 9 8 7
22 21 20 19
RIE REDIE REIE RPR
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-8 RCR_1 Register
DSP56367
Enhanced Serial Audio Interface 1 (ESAI_1)
ESAI_1 Programming Model
Receiver
Bit Clock Source
Reserved
SCKR_1
INT
SCKR_1 FSR_1
INT FSR_1
6 5 4
RSHFD RE3
18 17 16
RFSR RFSL RSWS4 RSWS3 RSWS2
OUTPUTS
SCKR_1
SCKR_1
3 2 1 0
RE2 RE1 RE0
15 14 13 12
11-11