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IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
When an upstream secondary bus reset occurs, the following sequence is executed.
1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with
the hot reset bit set.
2. All register fields in all registers associated with downstream ports, except those denoted as "sticky"
or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields
denoted as "sticky" or RWL is unaffected by an upstream secondary bus reset.
3. All TLPs received from downstream ports and queued in the PES4T4 are discarded.
4.
Logic in the stack, application layer, and switch core associated with the downstream ports are
gracefully reset.
5.
Wait for the Secondary Bus Reset (SRESET) bit in the upstream port's Switch Control Register
(SWCTL) to clear.
6. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and
Type 0 configuration read and write transactions that target the upstream port complete normally. During an
upstream secondary bus reset, all TLPs destined to the secondary side of the upstream port's PCI-to-PCI
bridge are treated as unsupported requests.
Downstream Secondary Bus Reset
A downstream secondary bus reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in the port's (i.e., port 0) Bridge Control
Register (BCTRL).
When a downstream secondary bus reset occurs, the following sequence is executed.
1.
If the corresponding downstream port's link is up, TS1 ordered sets with the hot reset bit set are
transmitted.
2. All TLPs received from corresponding downstream port and queued in the PES4T4 are discarded.
3.
Wait for the Secondary Bus Reset (SRESET) bit in the upstream port's Switch Control Register
(SWCTL) to clear.
4. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a downstream secondary bus reset. The operation
of other downstream ports is unaffected by a downstream secondary bus reset. During a downstream
secondary bus reset, Type 0 configuration read and write transactions that target the downstream port
complete normally. During a downstream secondary bus reset, all TLPs destined to the secondary side of
the downstream port's PCI-to-PCI bridge are treated as unsupported requests.
Downstream Port Reset Outputs
Individual downstream port reset outputs (P2RSTN through P4RSTN) are provided as GPIO pin alter-
nate functions. Following a fundamental reset, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs. The PES4T4 ensures through hardware that the minimum PxRSTN assertion
pulse width is no less than 200 µs.
Downstream port reset outputs can be configured to operate in one of three modes. These modes are:
power enable controlled reset output, power good controlled reset output, and hot reset controlled output.
The downstream port reset output mode is determined by the Reset Mode (RSTMODE) field in the Hot-
Plug Configuration Control (HPCFGCTL) register.
Power Enable Controlled Reset Output
In this mode, a downstream port reset output state is controlled as a side effect of the slot power being
turned on or off. The operation of this mode is illustrated in Figure 2.6. A downstream port's slot power is
controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register.
2 - 8
Clock Operation
February 1, 2011
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