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IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
Signal
CCLKDS
CCLKUS
RSTHALT
SWMODE[2:0]
APWRDISN
Reset
The PES4T4 defines four reset categories: fundamental reset, hot reset, upstream secondary bus reset,
and downstream secondary bus reset.
– A fundamental reset causes all logic in the PES4T4 to be returned to an initial state.
– A hot reset causes all logic in the PES4T4 to be returned to an initial state, but does not cause the
state of register fields denoted as "sticky" to be modified.
– An upstream secondary bus reset causes all devices on the virtual PCI bus to be hot reset except
the upstream port (i.e., upstream PCI to PCI bridge).
– A downstream secondary bus reset causes a hot reset to be propagated on the corresponding
external secondary bus link.
There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset is a fundamental reset that
occurs without the removal of power.
May Be
Overridden
Y
Common Clock Downstream. The assertion of this pin
indicates that all downstream ports are using the same
clock source as that provided to downstream devices.This
pin is used as the initial value of the Slot Clock Configura-
tion bit in all of the Link Status Registers for downstream
ports. The value may be overridden by modifying the SCLK
bit in the downstream port's PCIELSTS register.
Y
Common Clock Upstream. The assertion of this pin indi-
cates that the upstream port is using the same clock source
as the upstream device. This pin is used as the initial value
of the Slot Clock Configuration bit in the Link Status Regis-
ter for the upstream port. The value may be overridden by
modifying the SCLK bit in the upstream port's PCIELSTS
register.
Y
Reset Halt. When this signal is asserted during a PCI
Express fundamental reset, the PES4T4 executes the reset
procedure and remains in a reset state with the Master
SMBus active. This allows software to read and write regis-
ters internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT
bit is cleared in the SWCTL register through the SMBus
master.
The value may be overridden by modifying the RSTHALT
bit in the SWCTL register.
N
Switch Mode. These configuration pins determine the
PES4T4 switch operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initializa-
tion
0x2 - through 0xF Reserved
Y
Auxiliary Power Disable. If this signal is tied to logic '0'at
the bootup time then the device is disabled to use auxiliary
power and the associated logic on the chip is disabled. All
the FRSticky bit values are reset to the default values.
Table 2.1 Boot Configuration Vector Signals
2 - 4
Clock Operation
Description
February 1, 2011
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