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IDT PES4T4 Device Overview
Logic Diagram
Reference
Clocks
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 2
PCI Express
Switch
SerDes Input
Port 3
PCI Express
Switch
SerDes Input
Port 4
Master
SMBus Interface
System
Pins
SSID/SSVID
The PES4T4 contains the mechanisms necessary to implement the PCI-to-PCI bridge Subsystem ID and Subsystem Vendor ID capability struc-
ture. However, in the default configuration the Subsystem ID and Subsystem Vendor ID capability structure is not enabled. To enable this capability,
the SSID and SSVID fields in the Subsystem ID and Subsystem Vendor ID (SSIDSSVID) register must be initialized with the appropriate ID values.
the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to this capability. Finally, the Next Pointer
(NXTPTR) of this capability should be adjusted to point to the next capability if necessary.
Device Serial Number Enhanced Capability
The PES4T4 contains the mechanisms necessary to implement the PCI express device serial number enhanced capability. However, in the default
configuration this capability structure is not enabled. To enable the device serial number enhanced capability, the Serial Number Lower Doubleword
(SNUMLDW) and the Serial Number Upper Doubleword (SNUMUDW) registers should be initialized. The Next Pointer (NXTPTR) field in one of the
other enhanced capabilities should be initialized to point to this capability. Finally, the Next Pointer (NXTPTR) of this capability should be adjusted to
point to the next capability if necessary.
PES4T4 User Manual
PEREFCLKP
PEREFCLKN
PE0RP[0]
PE0RN[0]
PE2RP[0]
PE2RN[0]
PE3RP[0]
PE3RN[0]
PES4T4
PE4RP[0]
PE4RN[0]
MSMBCLK
MSMBDAT
CCLKDS
CCLKUS
RSTHALT
PERSTN
3
SWMODE[2:0]
WAKEN
APWRDISN
Figure 1.2 PES4T4 Logic Diagram
1 - 3
PCI Express
Switch
PE0TP[0]
SerDes Output
PE0TN[0]
Port 0
PCI Express
PE2TP[0]
Switch
SerDes Output
PE2TN[0]
Port 2
PCI Express
PE3TP[0]
Switch
SerDes Output
PE3TN[0]
Port 3
PCI Express
Switch
PE4TP[0]
SerDes Output
PE4TN[0]
Port 4
General Purpose
5
GPIO[9,7,2:0]
I/O
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG Pins
JTAG_TMS
JTAG_TRST_N
V
CORE
DD
V
I/O
DD
V
PE
DD
V
APE
DD
Power/Ground
V
SS
V
PE
TT
February 1, 2011
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