Internal Switch Error Control And Status Registers - Renesas IDT 89HPES4T4 User Manual

IDT Configuration Registers
Notes
PES4T4 User Manual
Bit Field
Type
Field Name
1 P2GPES RO
2 P3GPES RO
3 P4GPES RO
31:4 Reserved RO

Internal Switch Error Control and Status Registers

SWPECTL - Switch Parity Error Control (0x4D4)
Bit Field
Type
Field Name
0 DEEPC RW
1 GBEEP RW
7:2 Reserved RO
15:8 LENGTH RW
Default
Value
0x0 Port 2 General Purpose Event Status. When this bit is set,
the corresponding port is signalling a general purpose event
by asserting the GPEN signal. This bit is never set if the cor-
responding general purpose event is not enabled in the
GPECTL register.
GPEN is an alternate function of GPIO[7] and GPIO[7] is
asserted only if enabled to operate as an alternate function.
0x0 Port 3 General Purpose Event Status. When this bit is set,
the corresponding port is signalling a general purpose event
by asserting the GPEN signal. This bit is never set if the cor-
responding general purpose event is not enabled in the
GPECTL register.
GPEN is an alternate function of GPIO[7] and GPIO[7] is
asserted only if enabled to operate as an alternate function.
0x0 Port 4 General Purpose Event Status. When this bit is set,
the corresponding port is signalling a general purpose event
by asserting the GPEN signal. This bit is never set if the cor-
responding general purpose event is not enabled in the
GPECTL register.
GPEN is an alternate function of GPIO[7] and GPIO[7] is
asserted only if enabled to operate as an alternate function.
0x0 Reserved field.
Default
Value
0x0 Disable End-to-End Parity Checking. When this bit is set,
Sticky end-to-end parity is not checked by the port and errors are
never generated. End-to-end parity is always computed for
data sent by the port to the switch core and cannot be dis-
abled.
0x0 Generate Bad End-to-End Parity. When this bit is set, bad
Sticky parity is generated for all double words in TLPs emitted to
the switch core from this port (i.e., those received on the
ingress port or generated by the port) whose TLP header
length field (i.e., bits seven through zero of byte zero of the
TLP header) match the value in the Error Match Length
(Length) field in this register
0x0 Reserved field.
0x0 Error Match Length. When the GBEEP bit is set, bad parity
Sticky is generated for all double words in TLPs emitted to the
switch core from this port (i.e., those received on the ingress
port or generated by the stack) whose TLP header length
field (i.e., bits seven through zero of byte zero of the TLP
header) matches the value in this field.
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Description
Description
February 1, 2011