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IDT Power Management
Notes
PES4T4 User Manual
Power Express Power Management Fence Protocol
The Root complex takes the following steps to turn off power to a system:
– The root places all devices in the D3
– Upon entry to D3
, all devices transition their links to the L1 state
Hot
– The root broadcasts a PME_Turn_Off message
– Devices acknowledge the PME_Turn_Off message by returning a PME_TO_ACK message.
When the PES4T4 receives a PME_Turn_Off message it broadcasts the PME_Turn_Off message on all
active downstream ports. Prior to sending PME_TO_Ack response back, the upstream port starts aggre-
gating PME_TO_Ack response from all the downstream ports. After it has received a PME_TO_Ack
message on each of its downstream ports, the PES4T4 transmits a PME_TO_Ack message on its
upstream port and transitions its upstream link to L2/L3 Ready state.
The aggregation of PME_TO_Ack messages on downstream ports is abandoned when the upstream
port receives a TLP after receiving a PME_Turn_Off message on that port, but before it has responded with
a PME_TO_Ack message. Once a PME_TO_Ack message has been scheduled for transmission on the
upstream port, there is no need to abandon PME_TO_Ack aggregation, and received TLPs at that point
may be discarded.
If the TLP that causes PME_TO_Ack aggregation to be abandoned targets the PES4T4, the PES4T4
responds to the TLP normally. If the TLP that causes aggregation to be abandoned targets a downstream
port and the port is in L0, the TLP is transmitted on the downstream port. If the downstream port is not in L0
(i.e., it is in L2/L3 Ready), the switch transitions the link to Detect and then to L0. Once the link reaches L0,
the TLP is transmitted on the downstream port.
When PME_TO_Ack aggregation is abandoned, the PES4T4 makes no attempt to abandon the
PME_Turn_Off and PME_TO_Ack protocol on downstream ports. Devices downstream of the PES4T4 are
allowed to respond with a PME_TO_Ack and to transition to L2/L3 Ready. When the PES4T4 receives a
TLP (targeting switch or downstream devices) during the PME aggregation process, it waits for the arrival of
PME_TO_Ack from all the downstream ports before initiating link retraining on all the downstream ports.
The received TLP is sent to the destination port after the links retrain.
In order to avoid deadlock, a downstream port that does not receive a PME_TO_Ack message in the
time-out period specified in the PME_TO_Ack Time-Out (PMETOATO) field in the PME_TO_Ack Timer
(PMETOATIMER) register, declares a time-out, transitions its link to L2/L3 Ready state and signals to the
upstream port that a PME_TO_Ack message has been received. Upon receiving a PME_Turn_Off
message, the PES4T4 blocks the transmission of PM_PME messages. If instead of being transitioned to
the D3
state, the PES4T4 is transitioned to the D0
cold
of PM_PME messages.
Power Budgeting Capability
The PES4T4 contains the mechanisms necessary to implement the PCI express power budgeting
enhanced capability. However, by default, these mechanisms are not enabled. To enable the power
budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in
one of the other enhanced capabilities should be initialized to point to the power budgeting capability. The
Next Pointer (NXTPTR) of the power budgeting capability should be adjusted if necessary.
The power budgeting capability consists of the four power budgeting capability registers defined in the
PCIe 1.0a base specification and eight general purpose read-write registers. See section Power Budgeting
Enhanced Capability on page 9-49 for a description of these registers.
The Power Budgeting Capabilities (PWRBCAP) register contains the PCI express enhanced capability
header for the power budgeting capability. By default, this register has an initial read-only value of zero. To
enable the power budgeting capability, this register should be initialized via the serial EEPROM.
The Power Budgeting Data Value [0..9] (PWRBDV[0..9) registers are used to hold the power budgeting
information for that port in a particular operating condition. The PWRBDV registers may be read and written
when the Power Budgeting Data Value Unlock (PWRBDVUL) bit is set in the Switch Control (SWCTL)
state
Hot
state, then the PES4T4 resumes generation
uninitialized
7 - 3
February 1, 2011
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