Power Management; Introduction; Figure 7.1 Pes4T4 Power Management State Transition Diagram - Renesas IDT 89HPES4T4 User Manual

Notes
PES4T4 User Manual
®

Introduction

The PES4T4 supports the following device power management states: D0 Uninitialized, D0 Active,
D3 , and D3 . A power management state transition diagram for the states supported by the PES4T4
Hot Cold
is provided in Figure 7.1 and described in Table 7.1.
A power management capability structure is located in the configuration space of each PCI-PCI bridge
in the PES4T4. The power management capability structure associated with a PCI-PCI bridge of a down-
stream port only affects that port. Entering the D3
the L1 state. The power management capability structure associated with the upstream port (i.e., port 0)
affects the entire device. The PES4T4 supports the link Wakeup mechanism. It supports both in-band
Beacon signaling (transmission only, not detection) and side band WAKEN signaling. The Wakeup Protocol
requires the Vaux power supply to be ON.
The functional context is maintained in the D3
Power Management Control and Status Register (PMCSR) is set to 1. The internal logic and the contents of
the registers are maintained and the software is not required to re-initialize the device on transitions from
D3 to D0. Thus, the default value of the NOSOFTRST bit in the PMCSR register corresponds to the
Hot
functional context being maintained in the D3
Ready state regardless of the NOSOFTRST bit settings, and the software will have to re-initialize the
device.
Power-On Reset

Figure 7.1 PES4T4 Power Management State Transition Diagram

Power Management

state allows the link associated with the bridge to enter
Hot
state if the No_Soft_Reset (NOSOFTRST) bit in the
Hot
state. However, the device is reset if the link enters L2/L3
Hot
D0
Uninitialized
D0
Active
D3
hot
D3
cold
7 - 1
Chapter 7
Wakeup Protocol
February 1, 2011