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IDT Hot-Plug and Hot-Swap
Notes
PES4T4 User Manual
When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the
Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register,
then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This
occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control
(PCIESCTL) register. The state of a port's Power Fault (PxPFN) input is not latched by the PES4T4. For
proper operation, the system designer should ensure that once the PxPFN signal is asserted, it remains
asserted until the power enable (PxPEP) signal is toggled. This is required adapter behavior for the PCI
Express ExpressModule form factor.
Downstream port reset outputs are described in section Downstream Port Reset Outputs on page 2-8.
The default value of hot-plug registers following a hot or fundamental reset may be configured via serial
EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization,
the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result
of serial EEPROM initialization.
Hot-Plug I/O Expander
The PES4T4 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface
for hot-plug related signals associated with downstream ports. See section I/O Expanders on page 6-5 for
details on the operation of the I/O expanders and for the mapping of downstream hot-plug signals to I/O
expander inputs and outputs.
Hot-Plug Interrupts and Wake-up
The hot-plug controller associated with a downstream slot may generate an interrupt or wakeup event.
Hot-plug interrupts are only generated when the Hot Plug Interrupt Enable (HPIE) bit is set in the corre-
sponding port's PCI Express Slot Control (PCIESCTL) register.
The following bits, when set in the PCI Express Slot Status (PCIESSTS) register, generate an interrupt if
not masked by the corresponding bit in the PCI Express Slot Control (PCIESCTL) register or by the HPIE
bit: the Attention Button Pressed (ABP), Power Fault Detected (PFD), MRL Sensor Changed (MRLSC),
Presence Detected Changed (PDC), and Command Completed (CC).
When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable
(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command
(PCICMD) register. When the downstream port or the entire switch is in a D3
controller generates a wakeup event using a PM_PME message instead of an interrupt if the event interrupt
is not masked in the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE bit. If
the event interrupt is not masked and hot-plug interrupts are enabled, both a PM_PME and an interrupt are
generated. If the event interrupt is masked, neither a PM_PME nor interrupt are generated. Note that a
command completed (CC bit) interrupt will not generate a wakeup event.
Legacy System Hot-Plug Support
Some systems require support for operating systems that lack PCIe hot-plug support. The PES4T4
supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of
GPIO[7] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hot-
plug. Associated with each downstream port's hot-plug controller is a bit in the General Purpose Event
Control (P0_GPECTL) register. When this bit is set, then the corresponding PCIe base 1.1 hot-plug event
notification mechanisms are disabled for that port and INTx, MSI and PME events will not be generated by
that port due to hot-plug events. Instead, hot-plug events are signaled through assertion of the GPEN
signal. GPEN is an alternate function of GPIO[7], and GPIO[7] will not be asserted when GPEN is asserted
unless it is configured to operate as an alternate function.
Whenever a port signals a hot-plug event through assertion of the GPEN signal, the corresponding
port's status bit in the General Purpose Event Status (P0_GPESTS) register is set. A bit in the P0_GPESTS
register can only be set if the corresponding port's hot-plug controller is configured to signal hot-plug events
using the general purpose event (GPEN) signal assertion mechanism.
8 - 4
state, the hot-plug
Hot
February 1, 2011
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