Power Good Controlled Reset Output; Figure 2.6 Power Enable Controlled Reset Output Mode Operation; Figure 2.7 Power Good Controlled Reset Output Mode Operation - Renesas IDT 89HPES4T4 User Manual

IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
PxPEP
PxRSTN

Figure 2.6 Power Enable Controlled Reset Output Mode Operation

While slot power is disabled, the corresponding downstream port reset output is asserted.
When slot power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is
asserted and then power to the slot is enabled and the corresponding downstream port reset output is
negated. The time between the assertion of the PxPEP signal and the negation of the PxRSTN signal is
controlled by the value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.
While slot power is enabled, the corresponding downstream port reset output is negated.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.

Power Good Controlled Reset Output

As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is
controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on
the power good state of the slot's power supply. The operation of this mode is illustrated in Figure 2.7.
PxPEP
PxPWRGDN
PxRSTN

Figure 2.7 Power Good Controlled Reset Output Mode Operation

The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that
when power is enabled, the negation of the corresponding port reset output occurs as a result of and after
assertion of the slot's Power Good (PxPWRGDN) signal is observed. The time between the assertion of the
PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to
Reset Negation (PWR2RST) field in the HPCFGCTL register.
When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset
output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.
T
PWR2RST
T
PWR2RST
2 - 9
Clock Operation
T
RST2PWR
T
RST2PWR
February 1, 2011