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IDT Clocking, Reset, and Initialization
Notes
PES4T4 User Manual
If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is
detected (i.e., PxPWRGDN is negated), the corresponding port reset output is immediately asserted. Since
the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profiled power level
invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter
time interval may implement this functionality external to the PES4T4.
Hot Reset Controlled Reset Output
In this mode the following conditions cause a downstream port's reset output to be asserted.
– Hot reset
– Upstream secondary bus reset
– Downstream secondary bus reset
When a downstream port reset output is asserted it remains asserted as long as one of the above condi-
tions persists or 200 µs, whichever is longer.
2 - 10
Clock Operation
February 1, 2011
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