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IDT Link Operation
Notes
PES4T4 User Manual
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.
Upstream Port
When a Set_Slot_Power_Limit message is received by the upstream switch port, the fields in the
message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale
(CSPLS) field.
– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value
(CSPLV) field.
Downstream Port
A Set_Slot_Power_Limit message is sent by downstream switch ports when either of the following
events occur.
– A configuration write is performed to the corresponding PCIESCAP register when the link associ-
ated with the downstream port is up.
– A link associated with the downstream port transitions from a non-operational state to an opera-
tional (i.e., up) state.
Link States
The PES4T4 supports the following link states:
– L0
Fully operational link state
– L0s
Automatically entered low power state with shortest exit latency
– L1
Lower power state than L0s
May be automatically entered or directed by software by placing the device in the D3
– L2/L3 Ready
The L2/L3 state is entered after the acknowledgement of a PM_Turn_Off Message
There is no TLP or DLLP communications over a link in this state
– L2
The main power and reference clock are turned off but the auxiliary voltage is turned on. The
PES4T4 only exits this state when fundamental reset is applied (i.e., the PERSTN pin is asserted).
– L3
Link is completely unpowered and off
– Link Down
A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the LTSSM
Detect, Polling, Configuration, Disabled, Loopback, and Hot-Reset states.
4 - 2
state
hot
February 1, 2011
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