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8.1.2
Block Diagrams
16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA
to TIOCA
0
2
TIOCB
to TIOCB
0
2
Legend:
TSTR: Timer start register (8 bits)
TSNR: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TOLR: Timer output level setting register (8 bits)
TISRA: Timer interrupt status register A (8 bits)
TISRB: Timer interrupt status register B (8 bits)
TISRC: Timer interrupt status register C (8 bits)
Clock selector
Control logic
Module data bus
Figure 8.1 16-bit timer Block Diagram (Overall)
IMIA0 to IMIA2
IMIB0 to IMIB2
OVI0 to OVI2
TSTR
TSNR
TMDR
TOLR
TISRA
TISRB
TISRC
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