Block Diagrams - Hitachi F-ZTAT H8/3039 Series Hardware Manual

8.1.2 Block Diagrams

ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU.
TCLKA to TCLKD
ø, ø/2, ø/4, ø/8
TOCXA , TOCXB
4 4
TIOCA to TIOCA
0 4
TIOCB to TIOCB
0 4
Legend
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
188
Clock selector
Control logic
Module data bus
Figure 8-1 ITU Block Diagram (Overall)
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR