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2 Power Supply, Reset, and Clocks
The power supply, reset, and clocks in this IC are managed by the embedded power generator, system reset control-
ler, and clock generator, respectively.
2.1 Power Generator (PWG)
2.1.1 Overview
PWG is the power generator that controls the internal power supply system to drive this IC with stability and low
power. The main features of PWG are outlined below.
• Embedded V
regulator
D1
- The V
regulator generates the V
D1
consumption constant independent of the V
- The V
regulator supports two operation modes, normal mode and economy mode, and setting the V
D1
regulator into economy mode at light loads helps achieve low-power operations.
Figure 2.1.1.1 shows the PWG configuration.
V
DD
C
PW1
C
PW2
V
D1
V
SS
2.1.2 Pins
Table 2.1.2.1 lists the PWG pins.
Pin name
V
DD
V
SS
V
D1
For the V
operating voltage range and recommended external parts, refer to "Recommended Operating Condi-
DD
tions, Power supply voltage V
Diagram" chapter, respectively.
2.1.3 V
Regulator Operation Mode
D1
The V
regulator supports two operation modes, normal mode and economy mode. Setting the V
D1
economy mode at light loads helps achieve low-power operations. Table 2.1.3.1 lists examples of light load condi-
tions in which economy mode can be set.
Table 2.1.3.1 Examples of Light Load Conditions in which Economy Mode Can be Set
SLEEP mode (when all oscillators are stopped, or OSC1 only is active) When a clock source except for
HALT mode (when OSC1 only is active)
RUN mode (when OSC1 only is active)
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
voltage to drive internal circuits, this makes it possible to keep current
D1
voltage level.
DD
PWG
VD1ECO
V
D1
regulator
Figure 2.1.1.1 PWG Configuration
Table 2.1.2.1 List of PWG Pins
I/O
Initial status
P
–
P
–
A
–
" in the "Electrical Characteristics" chapter and the "Basic External Connection
DD
Light load condition
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
V
D1
Internal circuits
Function
Power supply (+)
GND
Embedded regulator output pin
OSC1 is active
D1
regulator into
D1
Exceptions
2-1
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